公开(公告)号：US07247946B2

公开(公告)日：2007-07-24

申请号：US11037970

申请日：2005-01-18

申请人： John Bruley ,  Roy A. Carruthers ,  Lynne Marie Gignac ,  Chao-Kun Hu ,  Eric Gerhard Liniger ,  Sandra Guy Malhotra ,  Stephen M. Rossnagel

发明人： John Bruley ,  Roy A. Carruthers ,  Lynne Marie Gignac ,  Chao-Kun Hu ,  Eric Gerhard Liniger ,  Sandra Guy Malhotra ,  Stephen M. Rossnagel

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76849 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Disclosed is a procedure to coat the free surface of Cu damascene lines by a 1-5 nm thick element prior to deposition of the inter-level dielectric or dielectric diffusion barrier layer. The coating provides protection against oxidation, increases the adhesion strength between the Cu and dielectric, and reduces interface diffusion of Cu. In addition, the thin cap layer further increases electromigration Cu lifetime and reduces the stress induced voiding. The selective elements can be directly deposited onto the Cu embedded within the under layer dielectric without causing an electric short circuit between the Cu lines. These chosen elements are based on their high negative reduction potentials with oxygen and water, and a low solubility in and formation of compounds with Cu.

摘要翻译： 公开了在沉积层间电介质或电介质扩散阻挡层之前，通过1-5nm厚的元件涂覆Cu镶嵌线的自由表面的步骤。 涂层提供防氧化保护，增加Cu和介电层之间的粘合强度，并减少Cu的界面扩散。 此外，薄盖层进一步增加电迁移Cu寿命，并减少应力引起的空隙。 选择元件可以直接沉积在嵌入在下层电介质中的Cu上，而不会在Cu线之间引起电短路。 这些选择的元素是基于它们具有氧和水的高的负还原电位，以及与Cu的化合物的低溶解度和形成。

公开(公告)号：US06380075B1

公开(公告)日：2002-04-30

申请号：US09676546

申请日：2000-09-29

申请人： Cyril Cabral, Jr. ,  Chao-Kun Hu ,  Sandra Guy Malhotra ,  Fenton Read McFeely ,  Stephen Mark Rossnagel ,  Andrew Herbert Simon

发明人： Cyril Cabral, Jr. ,  Chao-Kun Hu ,  Sandra Guy Malhotra ,  Fenton Read McFeely ,  Stephen Mark Rossnagel ,  Andrew Herbert Simon

IPC分类号： H01L214763

CPC分类号： H01L21/76844 ,  H01L21/28556 ,  H01L21/76859 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871

摘要： A method for forming an open-bottom liner for a conductor in an electronic structure and devices formed are disclosed. In the method, a pre-processed electronic substrate that has a dielectric layer on top is first provided. Via openings are then formed in a dielectric layer to expose an underlying conductive layer. The electronic substrate is then positioned in a cold-wall, low pressure chemical vapor deposition chamber, while the substrate is heated to a temperature of at least 350° C. A precursor gas is then flowed into the CVD chamber to a partial pressure of not higher than 10 mTorr, and metal is deposited from the precursor gas onto sidewalls of the via openings while bottoms of the via openings are substantially uncovered by the metal. The present invention method may be further enhanced by, optionally, modifications of a I-PVD technique or a seed layer deposition technique.

摘要翻译： 公开了一种用于形成电子结构中的导体的开口底部衬垫和形成的器件的方法。 在该方法中，首先提供在顶部具有电介质层的预处理电子基板。 然后在电介质层中形成通孔以暴露下面的导电层。 然后将电子基板定位在冷壁低压化学气相沉积室中，同时将基板加热至至少350℃的温度。然后将前体气体流入CVD室至不分压 高于10mTorr，并且金属从前体气体沉积到通孔开口的侧壁上，而通路孔的底部基本上不被金属覆盖。 本发明的方法可以通过任选地修饰I-PVD技术或种子层沉积技术进一步增强。

公开(公告)号：US07825516B2

公开(公告)日：2010-11-02

申请号：US10316484

申请日：2002-12-11

申请人： Stefanie Ruth Chiras ,  Michael Wayne Lane ,  Sandra Guy Malhotra ,  Fenton Reed Mc Feely ,  Robert Rosenberg ,  Carlos Juan Sambucetti ,  Philippe Mark Vereecken

发明人： Stefanie Ruth Chiras ,  Michael Wayne Lane ,  Sandra Guy Malhotra ,  Fenton Reed Mc Feely ,  Robert Rosenberg ,  Carlos Juan Sambucetti ,  Philippe Mark Vereecken

IPC分类号： H01L23/532

CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In integrated circuit technology; an electromigration and diffusion sensitive conductor of a metal such as copper and processing procedure therefore is provided, wherein, at a planarized chemical mechanical processed interfacing surface, the conductor metal is positioned in a region of a selectable low K eff dielectric material surrounded by a material selected to be protection from outdiffusion and a source of a film thickness cap that is to form over the conductor metal and/or serve as a catalytic layer for electroless selective deposition of a CoWP capping .

摘要翻译： 集成电路技术; 因此，提供了诸如铜的金属的电迁移和扩散敏感导体以及加工过程，其中在平坦化的化学机械处理的界面表面处，导体金属位于由材料包围的可选低K eff电介质材料的区域中 被选择为防止外扩散，以及在导体金属上形成的膜厚度源和/或用作CoWP封盖的无电选择性沉积的催化层。

公开(公告)号：US06660330B2

公开(公告)日：2003-12-09

申请号：US09829648

申请日：2001-04-10

申请人： Peter S. Locke ,  Sandra Guy Malhotra ,  Fenton Read McFeely ,  Andrew Herbert Simon ,  John Jacob Yurkas

发明人： Peter S. Locke ,  Sandra Guy Malhotra ,  Fenton Read McFeely ,  Andrew Herbert Simon ,  John Jacob Yurkas

IPC分类号： C23C1606

CPC分类号： C23C16/466 ,  C23C16/481 ,  H01L21/28556 ,  H01L21/67109

摘要： The present invention relates to a method and apparatus for ensuring uniform and reproducible heating of a deformation-tolerant substrate during low-pressure chemical vapor deposition (CVD) of a metal film on a surface of the substrate. The uniform and reproducible heating of the substrate is achieved in the present invention by positioning the substrate on a beveled surface of a chamfered ring which is located above the heating element in a CVD reactor chamber. The space between heating element, chamfered ring and bottom surface of the substrate define a cavity between the substrate and heating element that ensures that the substrate is heated by radiative means rather than direct contact.

摘要翻译： 本发明涉及一种在基板表面上的金属膜的低压化学气相沉积（CVD）期间确保变形耐受基板的均匀可重复加热的方法和装置。 在本发明中通过将衬底定位在位于CVD反应器室中的加热元件上方的倒角环的斜面上来实现衬底的均匀和可再现的加热。 加热元件，倒角环和衬底底面之间的空间限定了衬底和加热元件之间的空腔，确保衬底被辐射装置加热而不是直接接触。