公开(公告)号：US4414057A

公开(公告)日：1983-11-08

申请号：US446597

申请日：1982-12-03

申请人： Ronald R. Bourassa ,  Michael R. Reeder

发明人： Ronald R. Bourassa ,  Michael R. Reeder

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C23F1/02

CPC分类号： H01L21/32137

摘要： A process is described for anisotropically etching semiconductor products which include a lower dielectric layer, an intermediate polysilicon layer, and an upper silicide layer such as titanium silicide. A pattern-defining layer will normally overlie the silicide layer to define target areas to be etched. In a first step, the silicide is etched through using Freon 115 chloro, pentafluoroethane (C.sub.2 ClF.sub.5) in a plasma etching chamber conditioned to provide a reactive ion etch. The etch is completed in the same chamber using a second gas which includes an amount of Cl.sub.2 selected to etch anisotropically through the polysilicon layer without substantially etching the dielectric layer. Preferably, both etches occur after covering inner surfaces of the etching chamber with a material which releases molecules of the character included in the pattern-defining layer, such as Kapton, a polymide, in the disclosed example.

摘要翻译： 描述了各向异性蚀刻半导体产品的方法，其包括下介电层，中间多晶硅层和诸如硅化钛的上硅化物层。 图案定义层通常覆盖硅化物层以限定待蚀刻的靶区域。 在第一步中，通过在调节为提供反应离子蚀刻的等离子体蚀刻室中使用氟利昂115氯，五氟乙烷（C2ClF5）来蚀刻硅化物。 使用第二气体在相同的室中完成蚀刻，所述第二气体包括选择的量的各向异性蚀刻通过多晶硅层的Cl2，而基本上不蚀刻介电层。 优选地，在所揭示的实施例中，蚀刻室的内表面覆盖蚀刻室的内表面之后，使用释放包括在图案限定层中的字符分子的材料，例如Kapton，Polymide，发生蚀刻。

公开(公告)号：US4658378A

公开(公告)日：1987-04-14

申请号：US449984

申请日：1982-12-15

申请人： Ronald R. Bourassa

发明人： Ronald R. Bourassa

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/3215 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/04 ,  H01L29/86

CPC分类号： H01L28/20 ,  H01L21/32155 ,  H01L27/1112 ,  Y10S257/904

摘要： An improved load resistor for a VLSI memory cell is formed in polysilicon by having P-type (such as boron) impurities in a middle region and n-type (such as phosphorous or arsenic) impurities on the sides, with the concentrations being in a range so that the thermal activation energy is below about 0.5 eV. Further, the middle region can be doped additionally with arsenic or phosphorous in an amount equal to or less than the boron. This gives good leakage current masking over a range of -55.degree. to +125.degree. C. without drawing excessive current, and is less sensitive to impurities.

摘要翻译： 在多晶硅中通过在中间区域中具有P型（例如硼）杂质和在侧面上具有n型（例如磷或砷）杂质而形成用于VLSI存储单元的改进的负载电阻器，其浓度为 范围，使得热活化能低于约0.5eV。 此外，中间区域可以以等于或小于硼的量另外掺入砷或磷。 这样可以在-55°至+125°C的范围内实现良好的漏电流遮蔽，而不会产生过大的电流，并且对杂质的敏感性较差。

公开(公告)号：US4604789A

公开(公告)日：1986-08-12

申请号：US696918

申请日：1985-01-31

申请人： Ronald R. Bourassa

发明人： Ronald R. Bourassa

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  H01L21/822 ,  H01L21/425 ,  H01L21/44

CPC分类号： H01L28/20 ,  H01L21/321 ,  H01L21/76889

摘要： In making a polysilicon resistor in a polycide line, a thick oxide is established selectively to shield lightly doped polysilicon first from heavy doping and then from the silicide. Before adding silicide, a selected region of polysilicon broader than and including the site of the poly resistor is exposed, lightly doped, and then oxidized to establish a thick oxide, while other areas are protected by nitride. Then the nitride and any thin oxide on top of the polysilicon outside the broad area are removed, and the exposed polysilicon is heavily doped for low resistivity. The thick oxide shields the underlying lightly doped polysilicon from the heavy doping. Silicide is then added. Definition of the polysilicon resistor follows preferably using a two step process. When the silicide is etched, the thick oxide on top of the broad polysilicon area acts as an etch stop. Then the thick oxide and polysilicon resistor are etched.

摘要翻译： 在多晶硅线中制造多晶硅电阻器时，选择性地建立厚氧化物以首先从轻掺杂然后从硅化物屏蔽轻掺杂多晶硅。 在加入硅化物之前，比多晶硅电阻器的位置宽的多晶硅的选定区域被暴露，轻掺杂，然后被氧化以形成厚的氧化物，而其它区域被氮化物保护。 然后去除在宽区域外的多晶硅顶部的氮化物和任何薄氧化物，并且暴露的多晶硅被重掺杂以实现低电阻率。 厚氧化物屏蔽来自重掺杂的底层轻掺杂多晶硅。 然后加入硅化物。 多晶硅电阻的定义优选使用两步法。 当蚀刻硅化物时，宽多晶硅区域顶部的厚氧化物起蚀刻停止的作用。 然后蚀刻厚的氧化物和多晶硅电阻。

公开(公告)号：US4560419A

公开(公告)日：1985-12-24

申请号：US615166

申请日：1984-05-30

申请人： Ronald R. Bourassa ,  Douglas B. Butler

发明人： Ronald R. Bourassa ,  Douglas B. Butler

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/268 ,  H01L21/321 ,  H01L21/3215 ,  H01L21/324 ,  H01L21/822 ,  H01L27/11 ,  H01L21/263 ,  H01L21/26 ,  H01L21/425

CPC分类号： H01L21/324 ,  H01L21/2686 ,  H01L21/321 ,  H01L21/32155 ,  H01L28/20 ,  H01L27/1112 ,  Y10S257/904

摘要： An improved process in making a polysilicon resistor suitable for use as a load resistor in a static memory wherein after the doping of the polysilicon, the device is annealed by exposing it to a rapid increase of ambient temperature (up to between 900.degree. and 1200.degree. C.), maintaining the high ambient temperature for a controlled time (about 5 seconds) and then lowering the ambient temperature at a rapid rate. This decreases resistance by one order of magnitude and significantly decreases the temperature activation energy of the resistor. This permits static memory cells to retain data even though the cell has high leakage currents, thereby improving final test yields.

摘要翻译： 制造多晶硅电阻器的改进方法适合用作静态存储器中的负载电阻器，其中在掺杂多晶硅之后，通过使器件暴露于环境温度的快速增加（高达900°至1200°） C.），保持高的环境温度一段可控的时间（约5秒），然后以快速的速度降低环境温度。 这将电阻降低一个数量级并显着降低电阻器的温度激活能。 这允许静态存储单元保留数据，即使电池具有高泄漏电流，从而提高最终测试产量。

公开(公告)号：US4679170A

公开(公告)日：1987-07-07

申请号：US797050

申请日：1985-11-12

申请人： Ronald R. Bourassa ,  Douglas B. Butler

发明人： Ronald R. Bourassa ,  Douglas B. Butler

IPC分类号： H01L21/02 ,  H01L21/268 ,  H01L21/321 ,  H01L21/3215 ,  H01L21/324 ,  H01L27/11 ,  H01L27/04 ,  G11C11/40

CPC分类号： H01L28/20 ,  H01L21/2686 ,  H01L21/321 ,  H01L21/32155 ,  H01L21/324 ,  H01L27/1112 ,  Y10S257/904

摘要： An improved process in making a polysilicon resistor suitable for use as a load resistor in a static memory wherein after the doping of the polysilicon, the device is annealed by exposing it to a rapid increase of ambient temperature (up to between 900 and 1200.degree. C.), maintaining the high ambient temperature for a controlled time (about 5 seconds) and then lowering the ambient tempertature at a rapid rate. This decreases resistances by one order of magnitude and significantly decreases the temperature activation energy of the resistor. This permits static memory cells to retain data even though the cell has high leakage currents, thereby improving final test yields.

摘要翻译： 制造多晶硅电阻器的改进方法适用于静态存储器中的负载电阻器，其中在掺杂多晶硅之后，通过使器件暴露于环境温度的快速增加（高达900和1200℃） ），保持环境温度高于受控时间（约5秒），然后以较快速率降低环境温度。 这将电阻降低一个数量级并显着降低电阻器的温度激活能。 这允许静态存储单元保留数据，即使电池具有高泄漏电流，从而提高最终测试产量。

公开(公告)号：US4592128A

公开(公告)日：1986-06-03

申请号：US616921

申请日：1984-06-04

申请人： Ronald R. Bourassa

发明人： Ronald R. Bourassa

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/3215 ,  H01L21/822 ,  H01L21/22 ,  H01L21/306

CPC分类号： H01L28/20 ,  H01L21/321 ,  H01L21/32137 ,  H01L21/32155 ,  Y10S148/102

摘要： A poly layer on a substrate is covered with nitride. A reverse tone load implant mask and etch opens an area, which is then boron implanted. Controlled oxidation follows to grow oxide on the boron-doped region only, thereby thinning the poly there. Strip the nitride and then dope the poly layer. The oxide shields the boron-doped region from further substantial doping. Next, apply a poly definition photoresist mask. Etch the exposed oxide and poly to define a poly line having a boron-doped resistor therein. The difference in etch rates between heavily doped and lightly doped poly is compensated for by the adjustment of thickness of the boron-doped region. Hence, the etch for both types of poly concludes at about the same time, leaving the underlying layers substantially intact. Sources and drains may be implanted thereafter without an additional load implant mask.

摘要翻译： 衬底上的多层被氮化物覆盖。 反向色调负载注入掩模和蚀刻打开一个区域，然后硼被注入。 受控氧化仅在硼掺杂区域上生长氧化物，从而使聚硅氧烷变薄。 剥去氮化物，然后掺杂多层。 氧化物屏蔽硼掺杂区域进一步大量掺杂。 接下来，应用聚合物光刻胶掩模。 蚀刻暴露的氧化物和多晶，以限定其中具有掺杂硼的电阻器的多线。 通过调整硼掺杂区域的厚度来补偿重掺杂和轻掺杂多晶硅之间蚀刻速率的差异。 因此，两种类型的聚合物的蚀刻约在同一时间结束，使得下面的层基本上保持完整。 之后可以植入源和漏极，而不需要额外的负载注入掩模。