公开(公告)号：US20060273376A1

公开(公告)日：2006-12-07

申请号：US11145624

申请日：2005-06-06

Applicant: Ronald Weimer ,  Christopher Hill

Inventor： Ronald Weimer ,  Christopher Hill

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L29/42332

Abstract: A method is disclosed that may include forming a first layer of insulating material above a semiconducting substrate, forming an aluminum oxide layer above the first layer of insulating material, forming a plurality of spaced-apart dots of material on the aluminum oxide layer, forming a second layer of insulating material on portions of the aluminum oxide layer not covered by the spaced-apart dots of material, forming a conductive layer above the second layer of insulating material and the plurality of spaced-apart dots of material, and removing excess portions of the layer of conductive material and the second layer of insulating material. A device is disclosed that may include a substrate and a floating gate electrode positioned above a tunnel insulation layer, the floating gate electrode including a layer of insulating material and a plurality of spaced-apart dots of material, each of which have a conductive nano-dot positioned on the dot of material, the dots of material and the conductive nano-dots being positioned in the layer of insulating material.

Abstract translation: 公开了一种方法，其可以包括在半导体衬底上形成第一绝缘材料层，在第一绝缘材料层之上形成氧化铝层，在氧化铝层上形成多个间隔开的材料点，形成 第二层绝缘材料在不被间隔开的材料点覆盖的氧化铝层的部分上，在第二绝缘材料层上方形成导电层和多个间隔开的材料点，并且除去多余部分的绝缘材料 导电材料层和第二层绝缘材料。 公开了一种可以包括位于隧道绝缘层上方的衬底和浮置栅电极的器件，该浮栅电极包括一层绝缘材料和多个间隔开的点材料，每个点都具有导电的纳米 - 点位于材料点上，材料点和导电纳米点位于绝缘材料层中。

公开(公告)号：US20060213440A1

公开(公告)日：2006-09-28

申请号：US11430328

申请日：2006-05-09

Applicant: Lingyi Zheng ,  Trung Doan ,  Lyle Breiner ,  Er-Xuan Ping ,  Kevin Beaman ,  Ronald Weimer ,  David Kubista ,  Cem Basceri

Inventor： Lingyi Zheng ,  Trung Doan ,  Lyle Breiner ,  Er-Xuan Ping ,  Kevin Beaman ,  Ronald Weimer ,  David Kubista ,  Cem Basceri

IPC: C23C16/00

CPC classification number: C23C16/45546 ,  C23C16/45578 ,  C23C16/4583

Abstract: The present disclosure suggests several systems and methods for batch processing of microfeature workpieces, e.g., semiconductor wafers or the like. One exemplary implementation provides a method of depositing a reaction product on each of a batch of workpieces positioned in a process chamber in a spaced-apart relationship. A first gas may be delivered to an elongate first delivery conduit that includes a plurality of outlets spaced along a length of the conduit. A first gas flow may be directed by the outlets to flow into at least one of the process spaces between adjacent workpieces along a first vector that is transverse to the direction in which the workpieces are spaced. A second gas may be delivered to an elongate second delivery conduit that also has outlets spaced along its length. A second gas flow of the second gas may be directed by the outlets to flow into the process spaces along a second vector that is transverse to the first direction.

公开(公告)号：US20060204649A1

公开(公告)日：2006-09-14

申请号：US11418337

申请日：2006-05-04

Applicant: Kevin Beaman ,  Trung Doan ,  Lyle Breiner ,  Ronald Weimer ,  Er-Xuan Ping ,  David Kubista ,  Cem Basceri ,  Lingyi Zheng

Inventor： Kevin Beaman ,  Trung Doan ,  Lyle Breiner ,  Ronald Weimer ,  Er-Xuan Ping ,  David Kubista ,  Cem Basceri ,  Lingyi Zheng

IPC: C23C16/00 ,  C23C16/52

CPC classification number: C23C16/00 ,  C23C16/46

Abstract: The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.

Abstract translation: 本公开提供了用于控制温度的方法和系统。 该方法在沉积工艺中控制温度，例如通过CVD沉积热反射材料方面具有特别的用途。 一个示例性实施例提供了一种方法，其涉及监测沉积室外的第一温度和沉积室内的第二温度。 通过（a）将控制温度与目标温度进行比较，可以根据斜坡分布来增加沉积室中的内部温度，以及（b）响应于比较的结果，选择性地将热量输送到沉积室。 目标温度可以根据斜坡分布来确定，但是一个实现中的控制温度在第一温度和第二温度之间交替。

公开(公告)号：US20060030096A1

公开(公告)日：2006-02-09

申请号：US10913281

申请日：2004-08-06

Applicant: Ronald Weimer

Inventor： Ronald Weimer

IPC: H01L21/8238 ,  H01L29/76

CPC classification number: H01L21/823857 ,  H01L21/823842

Abstract: Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors are formed with an optional interfacial oxide, such as SiO2 or oxy-nitride, to overlay a semiconductor substrate which will be conductively doped for PMOS and NMOS regions. Then a dielectric possessing a high dielectric constant of least seven or greater (also referred to as a high-k dielectric) is deposited on the interfacial oxide. The high-k dielectric is covered with a thin monolayer of metal oxide (i.e., aluminum oxide, Al2O3) that is removed from the NMOS regions, but remains in the PMOS regions. The resulting NMOS transistor diffusion regions contain predominately metal to silicon bonds that create predominately Fermi level pinning near the valence band while the resulting PMOS transistor diffusion regions contain metal to silicon bonds that create predominately Fermi level pinning near the conduction band.

Abstract translation: 描述了在半导体组件上形成互补晶体管的互补晶体管和方法。 晶体管形成有可选的界面氧化物，例如SiO 2或氧化氮化物，以覆盖将被导电掺杂用于PMOS和NMOS区域的半导体衬底。 然后，在界面氧化物上沉积具有至少七个以上的高介电常数（也称为高k电介质）的电介质。 高k电介质覆盖有从NMOS区域去除的金属氧化物（即，氧化铝，Al 2 O 3 O 3）的薄单层，但保留在 PMOS区域。 所得到的NMOS晶体管扩散区域主要含有金属与硅键，其主要在价带附近产生费米能级钉扎，而所得的PMOS晶体管扩散区域含有金属与硅键，主要在导带附近产生费米能级钉扎。

公开(公告)号：US20050045102A1

公开(公告)日：2005-03-03

申请号：US10652461

申请日：2003-08-28

Applicant: Lingyi Zheng ,  Trung Doan ,  Lyle Breiner ,  Er-Xuan Ping ,  Kevin Beaman ,  Ronald Weimer ,  David Kubista ,  Cem Basceri

Inventor： Lingyi Zheng ,  Trung Doan ,  Lyle Breiner ,  Er-Xuan Ping ,  Kevin Beaman ,  Ronald Weimer ,  David Kubista ,  Cem Basceri

IPC: C23C16/44 ,  C23C16/455 ,  C23C16/458 ,  C23C16/00

CPC classification number: C23C16/45546 ,  C23C16/45578 ,  C23C16/4583

Abstract: The present disclosure suggests several systems and methods for batch processing of microfeature workpieces, e.g., semiconductor wafers or the like. One exemplary implementation provides a method of depositing a reaction product on each of a batch of workpieces positioned in a process chamber in a spaced-apart relationship. A first gas may be delivered to an elongate first delivery conduit that includes a plurality of outlets spaced along a length of the conduit. A first gas flow may be directed by the outlets to flow into at least one of the process spaces between adjacent workpieces along a first vector that is transverse to the direction in which the workpieces are spaced. A second gas may be delivered to an elongate second delivery conduit that also has outlets spaced along its length. A second gas flow of the second gas may be directed by the outlets to flow into the process spaces along a second vector that is transverse to the first direction.

Abstract translation: 本公开提出了用于批量处理微特征工件（例如半导体晶片等）的几种系统和方法。 一个示例性实施方案提供了一种在间隔开的关系中将反应产物沉积在处理室中的一批工件的每一个上的方法。 第一气体可以被输送到细长的第一输送管道，该第一输送管道包括沿管道的长度间隔开的多个出口。 第一气流可以由出口引导，沿着横向于工件间隔开的方向的第一向量流入相邻工件之间的至少一个工艺空间。 第二气体可以被输送到细长的第二输送管道，该第二输送管道也具有沿其长度间隔开的出口。 第二气体的第二气流可以由出口引导，沿着横向于第一方向的第二向量流入处理空间。

公开(公告)号：US20050039680A1

公开(公告)日：2005-02-24

申请号：US10646673

申请日：2003-08-21

Applicant: Kevin Beaman ,  Ronald Weimer ,  Lyle Breiner ,  Er-Xuan Ping ,  Trung Doan ,  Cem Basceri ,  David Kubista ,  Lingyi Zheng

Inventor： Kevin Beaman ,  Ronald Weimer ,  Lyle Breiner ,  Er-Xuan Ping ,  Trung Doan ,  Cem Basceri ,  David Kubista ,  Lingyi Zheng

IPC: C23C16/00 ,  C23C16/44 ,  C23C16/455

CPC classification number: C23C16/45546 ,  C23C16/4404

Abstract: The present disclosure provides methods and apparatus that may be used to process microfeature workpieces, e.g., semiconductor wafers. Some aspects have particular utility in depositing TiN in a batch process. One implementation involves pretreating a surface of a process chamber by contemporaneously introducing first and second pretreatment precursors (e.g., TiCl4 and NH3) to deposit a pretreatment material on a the chamber surface. After the pretreatment, the first microfeature workpiece may be placed in the chamber and TiN may be deposited on the microfeature workpiece by alternately introducing quantities of first and second deposition precursors.

Abstract translation: 本公开提供了可用于处理微特征工件（例如半导体晶片）的方法和装置。 一些方面在分批过程中沉积TiN具有特殊的用途。 一个实施方案包括通过同时引入第一和第二预处理前体（例如，TiCl 4和NH 3）在处理室表面上预沉积预处理材料来处理处理室的表面。 在预处理之后，可以将第一微特征工件放置在腔室中，并且可以通过交替地引入量的第一和第二沉积前体将TiN沉积在微特征工件上。

公开(公告)号：US20060289950A1

公开(公告)日：2006-12-28

申请号：US11513659

申请日：2006-08-31

Applicant: Ronald Weimer

Inventor： Ronald Weimer

IPC: H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC classification number: H01L21/28185 ,  H01L21/28061 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

Abstract: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing silicon onto an oxide substrate as a thin layer, and then thermally annealing the silicon layer in a nitrogen-containing species or exposing the silicon to a plasma source of nitrogen to nitridize the silicon layer.

公开(公告)号：US20060252207A1

公开(公告)日：2006-11-09

申请号：US11486527

申请日：2006-07-13

Applicant: Kevin Beaman ,  Ronald Weimer

Inventor： Kevin Beaman ,  Ronald Weimer

IPC: H01L21/336

CPC classification number: H01L21/28194 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/511 ,  H01L29/518

Abstract: The invention includes a method of forming a programmable memory device. A tunnel oxide is formed to be supported by a semiconductor substrate. A stack is formed over the tunnel oxide. The stack comprises a floating gate, dielectric mass and control gate. The stack has a top, and has opposing sidewalls extending downwardly from the top. The dielectric mass includes silicon nitride. Silicon nitride spacers are formed along sidewalls of the stack, and a silicon nitride cap is formed over a top of the stack. The silicon nitride within the dielectric mass, cap and/or sidewall spacers is formed from trichlorosilane and ammonia.

公开(公告)号：US20060205187A1

公开(公告)日：2006-09-14

申请号：US11430492

申请日：2006-05-09

Applicant: Lingyi Zheng ,  Trung Doan ,  Lyle Breiner ,  Er-Xuan Ping ,  Kevin Beaman ,  Ronald Weimer ,  David Kubista ,  Cem Basceri

Inventor： Lingyi Zheng ,  Trung Doan ,  Lyle Breiner ,  Er-Xuan Ping ,  Kevin Beaman ,  Ronald Weimer ,  David Kubista ,  Cem Basceri

IPC: H01L21/20

CPC classification number: C23C16/45546 ,  C23C16/45578 ,  C23C16/4583

Abstract: The present disclosure suggests several systems and methods for batch processing of microfeature workpieces, e.g., semiconductor wafers or the like. One exemplary implementation provides a method of depositing a reaction product on each of a batch of workpieces positioned in a process chamber in a spaced-apart relationship. A first gas may be delivered to an elongate first delivery conduit that includes a plurality of outlets spaced along a length of the conduit. A first gas flow may be directed by the outlets to flow into at least one of the process spaces between adjacent workpieces along a first vector that is transverse to the direction in which the workpieces are spaced. A second gas may be delivered to an elongate second delivery conduit that also has outlets spaced along its length. A second gas flow of the second gas may be directed by the outlets to flow into the process spaces along a second vector that is transverse to the first direction.

Abstract translation: 本公开提出了用于批量处理微特征工件（例如半导体晶片等）的几种系统和方法。 一个示例性实施方案提供了一种在间隔开的关系中将反应产物沉积在处理室中的一批工件的每一个上的方法。 第一气体可以被输送到细长的第一输送管道，该第一输送管道包括沿管道的长度间隔开的多个出口。 第一气流可以由出口引导，沿着横向于工件间隔开的方向的第一向量流入相邻工件之间的至少一个工艺空间。 第二气体可以被输送到细长的第二输送管道，该第二输送管道也具有沿其长度间隔开的出口。 第二气体的第二气流可以由出口引导，沿着横向于第一方向的第二向量流入处理空间。

公开(公告)号：US20060194446A1

公开(公告)日：2006-08-31

申请号：US11415320

申请日：2006-05-01

Applicant: Kevin Beaman ,  John Moore ,  Ronald Weimer

Inventor： Kevin Beaman ,  John Moore ,  Ronald Weimer

IPC: H01L23/52 ,  H01L21/31

CPC classification number: H01L21/28185 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28061 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/3144 ,  H01L29/518 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of adjusting the threshold voltage of semiconductor devices by incorporating nitride into the isolation layer so as to decrease the mobility of charge carriers and thereby increase the threshold voltage required to activate the device. The nitrogen incorporation method may comprise of decoupled plasma nitridization (DPN) and the DPN can be performed in-situ during gate oxide formation. The amount of threshold voltage can be varied by adjusting the DPN treatment time and processing parameters.

Abstract translation: 一种通过将氮化物结合到隔离层中来调节半导体器件的阈值电压的方法，以便降低电荷载流子的迁移率，从而增加激活器件所需的阈值电压。 氮掺杂方法可以包括去耦等离子体氮化（DPN），并且可以在栅极氧化物形成期间原位进行DPN。 可以通过调整DPN处理时间和处理参数来改变阈值电压量。