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    NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same
    5.
    发明授权
    NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same 有权
    NAND存储器阵列结合未选择的存储单元中的沟道区域的电容升压及其操作方法

    公开(公告)号：US07433233B2

    公开(公告)日：2008-10-07

    申请号：US11764793

    申请日：2007-06-18

    申请人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

    发明人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/3418 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1159

    摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

    摘要翻译： 示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。 为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。 此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。 在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

    System architecture and method for three-dimensional memory
    6.
    发明授权
    System architecture and method for three-dimensional memory 有权
    三维内存的系统架构和方法

    公开(公告)号：US07383476B2

    公开(公告)日：2008-06-03

    申请号：US10774758

    申请日：2004-02-09

    申请人： Matthew P. Crowley ,  Luca G. Fasoli ,  Alper Ilkbahar ,  Mark G. Johnson ,  Bendik Kleveland ,  Thomas H. Lee ,  Roy E. Scheuerlein

    发明人： Matthew P. Crowley ,  Luca G. Fasoli ,  Alper Ilkbahar ,  Mark G. Johnson ,  Bendik Kleveland ,  Thomas H. Lee ,  Roy E. Scheuerlein

    IPC分类号： G11C29/00 ,  G11C11/00

    CPC分类号： G06F11/1008 ,  G11C7/22 ,  G11C17/00

    摘要： In one embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array and at least two of the following system blocks: an Error Checking & Correction Circuit (ECC); a Checkerboard Memory Array containing sub arrays; a Write Controller; a Charge Pump; a Vread Generator; an Oscillator; a Band Gap Reference Generator; and a Page Register/Fault Memory. In another embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array, ECC, and smart write. The monolithic three-dimensional write-once memory array comprises a first conductor, a first memory cell above the first conductor, a second conductor above the first memory cell, and a second memory cell above the second conductor, wherein the second conductor is the only conductor between the first and second memory cells.

    摘要翻译： 在一个实施例中，提供了包括单片三维一次写入存储器阵列和以下系统块中的至少两个的芯片级结构：错误检查和校正电路（ECC）; 包含子数组的棋盘存储器阵列; 写控制器 电荷泵; Vread发生器; 振荡器 带隙参考发生器; 和页面寄存器/故障存储器。 在另一个实施例中，提供了包括单片三维一次写入存储器阵列ECC和智能写入的芯片级架构。 单片三维一次写入存储器阵列包括第一导体，第一导体上方的第一存储单元，第一存储单元上方的第二导体和第二导体上方的第二存储单元，其中第二导体是唯一的 第一和第二存储单元之间的导体。

    Redundant memory structure using bad bit pointers
    7.
    发明授权
    Redundant memory structure using bad bit pointers 有权
    冗余内存结构使用坏位指针

    公开(公告)号：US06996017B2

    公开(公告)日：2006-02-07

    申请号：US10961501

    申请日：2004-10-08

    申请人： Roy E. Scheuerlein ,  Mark G. Johnson ,  Derek J. Bosch ,  Alper Ilkbahar ,  J. James Tringali

    发明人： Roy E. Scheuerlein ,  Mark G. Johnson ,  Derek J. Bosch ,  Alper Ilkbahar ,  J. James Tringali

    IPC分类号： G11C7/00

    CPC分类号： G11C29/76 ,  G11C7/1006 ,  G11C7/24 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/78

    摘要： The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

    摘要翻译： 这里描述的优选实施例涉及使用坏比特指针的冗余存储器结构。 在一个优选实施例中，将数据写入第一多个存储单元，并且在存储单元之一中写入数据时检测到错误。 响应于检测到的错误，指针被写入第二多个存储单元中，该指针标识第一多个存储单元中的哪个存储单元包含该错误。 在读操作期间，从第一多个存储单元读取数据，并从第二多个存储单元读取指针。 从指针中，识别包含错误的存储单元，并纠正错误。 提供了其它优选实施方案，并且每个优选实施方案可以单独使用或彼此组合使用。

    Integrated systems using vertically-stacked three-dimensional memory cells
    8.
    发明授权
    Integrated systems using vertically-stacked three-dimensional memory cells 有权
    使用垂直堆叠的三维存储单元的集成系统

    公开(公告)号：US06765813B2

    公开(公告)日：2004-07-20

    申请号：US10185588

    申请日：2002-06-27

    申请人： Roy E. Scheuerlein ,  J. James Tringali ,  Colm P. Lysaght ,  Alper Ilkbahar ,  Christopher S. Moore ,  David R. Friedman

    发明人： Roy E. Scheuerlein ,  J. James Tringali ,  Colm P. Lysaght ,  Alper Ilkbahar ,  Christopher S. Moore ,  David R. Friedman

    IPC分类号： G11C502

    CPC分类号： G11C5/025 ,  G11C5/063 ,  G11C2213/71

    摘要： Support circuitry for a three-dimensional memory array is formed in a substrate at least partially under the three-dimensional memory array and defines open area in the substrate under the three-dimensional memory array. In one preferred embodiment, one or more memory arrays are formed at least partially in the open area under the three-dimensional memory array, while in another preferred embodiment, logic circuitry implementing one or more functions is formed at least partially in the open area under the three-dimensional memory array. In yet another preferred embodiment, both one or more memory arrays and logic circuitry are formed at least partially in the open area under the three-dimensional memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

    摘要翻译： 用于三维存储器阵列的支持电路至少部分地在三维存储器阵列的下方形成在衬底中，并且在三维存储器阵列下的衬底中限定开放区域。 在一个优选实施例中，至少部分地在三维存储器阵列下的开放区域中形成一个或多个存储器阵列，而在另一个优选实施例中，实现一个或多个功能的逻辑电路至少部分地形成在开放区域 三维记忆阵列。 在另一优选实施例中，一个或多个存储器阵列和逻辑电路至少部分地形成在三维存储器阵列下方的开放区域中。 提供了其它优选实施方案，并且每个优选实施方案可以单独使用或彼此组合使用。

    NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same
    10.
    发明授权
    NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same 有权
    NAND存储器阵列结合未选择的存储单元中的沟道区域的电容升压及其操作方法

    公开(公告)号：US07233522B2

    公开(公告)日：2007-06-19

    申请号：US10729831

    申请日：2003-12-05

    申请人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

    发明人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3418 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1159

    摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

    摘要翻译： 示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。 为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。 此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。 在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。