公开(公告)号：US06629291B1

公开(公告)日：2003-09-30

申请号：US09668977

申请日：2000-09-25

申请人： Russell J. Houghton ,  Joni C. Hsu ,  Louis L. Hsu ,  Li-Kong Wang

发明人： Russell J. Houghton ,  Joni C. Hsu ,  Louis L. Hsu ,  Li-Kong Wang

IPC分类号： G06F1750

CPC分类号： G06F1/28 ,  G06F17/5045 ,  G11C5/14

摘要： A centralized power supply system for a multi-system on chip device includes: an external power supply for supplying power to the device; a centralized DC generator macro having generator components for receiving the external power supplied and generating therefrom one or more power supply voltages for use by surrounding system macros provided on the multi-system chip, the centralized DC generator macro further distributing the generated power supply voltages to respective system macros. A noise blocking structure is provided that surrounds the centralized DC generator system and isolates the centralized DC generator system from the surrounding system macros.

摘要翻译： 一种用于多系统片上设备的集中供电系统包括：用于向设备供电的外部电源; 集中式DC发电机宏，其具有用于接收所提供的外部电力并由其产生的一个或多个电源电压，用于由多系统芯片上提供的周围系统宏使用的发电机组件，集中式DC发电机宏进一步将生成的电源电压分配到 各自的系统宏。 提供了围绕集中式DC发电机系统的隔离结构，并将集中式DC发电机系统与周围系统宏隔离开来。

公开(公告)号：US06337595B1

公开(公告)日：2002-01-08

申请号：US09627599

申请日：2000-07-28

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Russell J. Houghton ,  Wayne F. Ellis ,  Jeffrey H. Dreibelbis

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Russell J. Houghton ,  Wayne F. Ellis ,  Jeffrey H. Dreibelbis

IPC分类号： G05F302

CPC分类号： G05F3/265

摘要： A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e.g., one volt to 1.5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e.g., from 1.5 volts to about 2.5 volts, for operating a boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt. A one-volt negative voltage pump circuit is also included for pumping the voltages of at least one corresponding charge pump circuit, even when an operating voltage of the DC generator system is at or near one-volt. The DC voltage generator system is specifically designed to be implemented within battery-operated devices having at least one memory unit. The low-power consumption feature of the DC voltage generator system extends battery lifetime and data retention time of the cells of the at least one memory unit.

公开(公告)号：US06531911B1

公开(公告)日：2003-03-11

申请号：US09611519

申请日：2000-07-07

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Russell J. Houghton

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Russell J. Houghton

IPC分类号： H01L3500

CPC分类号： G05F3/30 ,  G01K7/015 ,  H01L23/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A combined low-voltage, low-power band-gap reference and temperature sensor circuit is provided for providing a band-gap reference parameter and for sensing the temperature of a chip, such as an eDRAM memory unit or CPU chip, using the band-gap reference parameter. The combined sensor circuit is insensitive to supply voltage and a variation in the chip temperature. The power consumption of both circuits, i.e., the band-gap reference and the temperature sensor circuits, encompassing the combined sensor circuit is less than one &mgr;W. The combined sensor circuit can be used to monitor local or global chip temperature. The result can be used to (1) regulate DRAM array refresh cycle time, e.g., the higher the temperature, the shorter the refresh cycle time, (2) to activate an on-chip or off-chip cooling or heating device to regulate the chip temperature, (3) to adjust internally generated voltage level, and (4) to adjust the CPU (or microprocessor) clock rate, i.e., frequency, so that the chip will not overheat. The combined band-gap reference and temperature sensor circuit of the present invention can be implemented within battery-operated devices having at least one memory unit. The low-power circuits of the sensor circuit extend battery lifetime and data retention time of the cells of the at least one memory unit.

摘要翻译： 提供了组合的低压，低功率带隙参考和温度传感器电路，用于提供带隙参考参数，并且用于使用频带参考参数来感测诸如eDRAM存储器单元或CPU芯片的芯片的温度， 间隙参考参数。 组合的传感器电路对电源电压和芯片温度的变化不敏感。 包含组合传感器电路的两个电路（即带隙基准和温度传感器电路）的功耗小于1μW。 组合传感器电路可用于监测局部或全局芯片温度。 结果可用于（1）调节DRAM阵列刷新周期时间，例如温度越高，刷新周期时间越短，（2）启动片上或片外冷却或加热装置来调节 芯片温度，（3）调节内部产生的电压电平，（4）调整CPU（或微处理器）的时钟频率，即频率，使芯片不会过热。 本发明的组合带隙参考和温度传感器电路可以在具有至少一个存储器单元的电池供电的装置内实现。 传感器电路的低功率电路延长了至少一个存储器单元的单元的电池寿命和数据保持时间。

公开(公告)号：US06507237B2

公开(公告)日：2003-01-14

申请号：US10039874

申请日：2002-01-03

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Russell J. Houghton ,  Wayne F. Ellis ,  Jeffrey H. Dreibelbis

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Russell J. Houghton ,  Wayne F. Ellis ,  Jeffrey H. Dreibelbis

IPC分类号： G05F110

CPC分类号： G05F3/265

摘要： A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e.g., one volt to 1.5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e.g., from 1.5 volts to about 2.5 volts, for operating a boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt. A one-volt negative voltage pump circuit is also included for pumping the voltages of at least one corresponding charge pump circuit, even when an operating voltage of the DC generator system is at or near one-volt. The DC voltage generator system is specifically designed to be implemented within battery-operated devices having at least one memory unit. The low-power consumption feature of the DC voltage generator system extends battery lifetime and data retention time of the cells of the at least one memory unit.

公开(公告)号：US06876250B2

公开(公告)日：2005-04-05

申请号：US10345039

申请日：2003-01-15

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Russell J. Houghton

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Russell J. Houghton

IPC分类号： G01K7/01 ,  G05F3/30 ,  H01L23/34 ,  G05F1/10

CPC分类号： G05F3/30 ,  G01K7/015 ,  H01L23/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A combined low-voltage, low-power band-gap reference and temperature sensor circuit is provided for providing a band-gap reference parameter and for sensing the temperature of a chip, such as an eDRAM memory unit or CPU chip, using the band-gap reference parameter. The combined sensor circuit is insensitive to supply voltage and a variation in the chip temperature. The power consumption of both circuits, i.e., the band-gap reference and the temperature sensor circuits, encompassing the combined sensor circuit is less than one μW. The combined sensor circuit can be used to monitor local or global chip temperature. The result can be used to (1) regulate DRAM array refresh cycle time, e.g., the higher the temperature, the shorter the refresh cycle time, (2) to activate an on-chip or off-chip cooling or heating device to regulate the chip temperature, (3) to adjust internally generated voltage level, and (4) to adjust the CPU (or microprocessor) clock rate, i.e., frequency, so that the chip will not overheat. The combined band-gap reference and temperature sensor circuit of the present invention can be implemented within battery-operated devices having at least one memory unit. The low-power circuits of the sensor circuit extend battery lifetime and data retention time of the cells of the at least one memory unit.

摘要翻译： 提供了组合的低压，低功率带隙参考和温度传感器电路，用于提供带隙参考参数，并且用于使用频带参考参数来感测诸如eDRAM存储器单元或CPU芯片的芯片的温度， 间隙参考参数。 组合的传感器电路对电源电压和芯片温度的变化不敏感。 包含组合传感器电路的两个电路（即带隙基准和温度传感器电路）的功耗小于1μW。 组合传感器电路可用于监测局部或全局芯片温度。 结果可用于（1）调节DRAM阵列刷新周期时间，例如温度越高，刷新周期时间越短，（2）启动片上或片外冷却或加热装置来调节 芯片温度，（3）调节内部产生的电压电平，（4）调整CPU（或微处理器）的时钟频率，即频率，使芯片不会过热。 本发明的组合带隙参考和温度传感器电路可以在具有至少一个存储器单元的电池供电的装置内实现。 传感器电路的低功率电路延长了至少一个存储器单元的单元的电池寿命和数据保持时间。

公开(公告)号：US07052937B2

公开(公告)日：2006-05-30

申请号：US10429758

申请日：2003-05-05

申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsorng-Dih Yuan

发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsorng-Dih Yuan

IPC分类号： H01L21/44

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L23/3677 ,  H01L23/3732 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure. Yet another embodiment comprises diamond sidewalls formed along the device walls in thermal contact with the device junctions to provide heat dissipation through the device junctions to underlying cooling structures. It is also proposed that the foregoing structures, and combinations of the foregoing structures, could be used in conjunction with other known cooling schemes.

公开(公告)号：US07029956B2

公开(公告)日：2006-04-18

申请号：US10666972

申请日：2003-09-19

申请人： Louis L. Hsu ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Li-Kong Wang

IPC分类号： H01L21/332

CPC分类号： H01L27/1027 ,  H01L21/8213 ,  H01L27/0605 ,  Y10S438/931

摘要： A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.

公开(公告)号：US06911375B2

公开(公告)日：2005-06-28

申请号：US10452715

申请日：2003-06-02

申请人： Kathryn W. Guarini ,  Louis L. Hsu ,  Leathen Shi ,  Dinkar V. Singh ,  Li-Kong Wang

发明人： Kathryn W. Guarini ,  Louis L. Hsu ,  Leathen Shi ,  Dinkar V. Singh ,  Li-Kong Wang

IPC分类号： H01L21/30 ,  H01L21/68 ,  H01L21/762

CPC分类号： H01L21/76256 ,  H01L21/6835 ,  H01L21/76254 ,  H01L2221/68368 ,  H01L2924/19041

摘要： Described is a method for making silicon on sapphire structures, and devices therefrom. The inventive method of forming integrated circuits on a sapphire substrate comprises the steps of providing a device layer on an oxide layer of a temporary substrate; bonding the device layer to a handling substrate; removing the temporary substrate to provide a structure containing the device layer between the oxide layer and the handling substrate; bonding a sapphire substrate to the oxide layer; removing the handling substrate from the structure; and annealing the final structure to provide a substrate comprising the oxide layer between the device layer and the sapphire substrate. The sapphire substrate may comprise bulk sapphire or may be a conventional substrate material with an uppermost sapphire layer.

摘要翻译： 描述了在蓝宝石结构上制造硅的方法及其装置。 在蓝宝石衬底上形成集成电路的本发明的方法包括以下步骤：在临时衬底的氧化物层上提供器件层; 将所述器件层接合到处理衬底; 去除所述临时衬底以提供在所述氧化物层和所述处理衬底之间包含所述器件层的结构; 将蓝宝石衬底结合到氧化物层; 从结构中去除处理基板; 并退火最终结构以提供包括在器件层和蓝宝石衬底之间的氧化物层的衬底。 蓝宝石衬底可以包括散装蓝宝石，或者可以是具有最上层蓝宝石层的常规衬底材料。

公开(公告)号：US06781185B2

公开(公告)日：2004-08-24

申请号：US10091193

申请日：2002-03-05

申请人： Howard Hao Chen ,  Louis L. Hsu ,  Li-Kong Wang

发明人： Howard Hao Chen ,  Louis L. Hsu ,  Li-Kong Wang

IPC分类号： H01L27108

CPC分类号： H01L28/91 ,  H01L23/5222 ,  H01L27/0805 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： Apparatus and method for providing high dielectric constant decoupling capacitors for semiconductor structures. The high dielectric constant decoupling capacitor can be fabricated by depositing high dielectric constant material between adjacent conductors on the same level, between conductors in successive levels, or both, to thereby provide very large capacitance value without any area or reliability penalty.

摘要翻译： 用于为半导体结构提供高介电常数去耦电容器的装置和方法。 高介电常数去耦电容器可以通过在相同电平上的相邻导体之间，连续电平的导体之间沉积高介电常数材料或两者来制造，从而提供非常大的电容值而没有任何面积或可靠性损失。

公开(公告)号：US06697909B1

公开(公告)日：2004-02-24

申请号：US09660431

申请日：2000-09-12

申请人： Li-Kong Wang ,  Louis L. Hsu

发明人： Li-Kong Wang ,  Louis L. Hsu

IPC分类号： G06F1300

CPC分类号： G11C11/40603 ,  G06F12/0802 ,  G11C11/406 ,  G11C11/40607

摘要： A method and apparatus for refreshing data in a dynamic random access memory (DRAM) cache memory in a computer system are provided to perform a data refresh operation without refresh penalty (e.g., delay in a processor). A data refresh operation is performed with respect to a DRAM cache memory by detecting a request address from a processor, stopping a normal refresh operation when the request address is detected, comparing the request address with TAG addresses stored in a TAG memory, generating refresh addresses to refresh data stored in the cache memory, each of which is generated based on an age of data corresponding to the refresh address, and performing a read/write operation on a wordline accessed by the request addresses and refreshing data on wordlines accessed by the refresh addresses, wherein the read/write operation and the refreshing of data are performed simultaneously.

摘要翻译： 提供了一种用于刷新计算机系统中的动态随机存取存储器（DRAM）高速缓冲存储器中的数据的方法和装置，用于执行数据刷新操作而不刷新（例如处理器中的延迟）。 通过检测来自处理器的请求地址，当检测到请求地址时停止正常刷新操作，将请求地址与存储在TAG存储器中的TAG地址进行比较，生成刷新地址 刷新存储在高速缓冲存储器中的数据，其中每个基于与刷新地址相对应的数据的年龄生成，并且对由请求地址访问的字线执行读/写操作，并且通过刷新访问的字线刷新数据 地址，其中同时执行读/写操作和数据刷新。