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    Method and structure for providing improved thermal conduction for silicon semiconductor devices
    3.
    发明授权
    Method and structure for providing improved thermal conduction for silicon semiconductor devices 失效

    公开(公告)号：US07052937B2

    公开(公告)日：2006-05-30

    申请号：US10429758

    申请日：2003-05-05

    申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsorng-Dih Yuan

    发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsorng-Dih Yuan

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L23/3677 ,  H01L23/3732 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure. Yet another embodiment comprises diamond sidewalls formed along the device walls in thermal contact with the device junctions to provide heat dissipation through the device junctions to underlying cooling structures. It is also proposed that the foregoing structures, and combinations of the foregoing structures, could be used in conjunction with other known cooling schemes.

    Structure and method for shadow mask electrode
    7.
    发明授权
    Structure and method for shadow mask electrode 有权
    荫罩电极的结构和方法

    公开(公告)号：US06768063B2

    公开(公告)日：2004-07-27

    申请号：US09943827

    申请日：2001-08-31

    申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

    发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

    IPC分类号： H05K111

    CPC分类号： H05K3/24 ,  G01N27/226 ,  H01L23/4824 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and structure for an electrode device, whereby a second electrode is deposited on a first electrode such that there is an increase in the capacitive coupling between the pair of conductive electrodes. The electrodes are self-aligning such that the patterning manufacturing process is insensitive to variations in the positional placement of the pattern on the substrate. Moreover, a single lithographic masking layer is used for forming the pair of electrodes, which are electrically isolated. Finally, the first electrode is offset from the second electrode by a chemical surface modification of the first electrode, and an anisotropic deposition of the second electrode which is shadowed by the first electrode.

    摘要翻译： 一种电极装置的方法和结构，由此第二电极沉积在第一电极上，使得一对导电电极之间的电容耦合增加。 电极是自对准的，使得图案化制造工艺对图案在衬底上的位置放置的变化不敏感。 此外，单个光刻掩模层用于形成电隔离的一对电极。 最后，第一电极通过第一电极的化学表面改性和由第一电极遮蔽的第二电极的各向异性沉积而偏离第二电极。

    Method of forming a planar polymer transistor using substrate bonding techniques
    8.
    发明授权
    Method of forming a planar polymer transistor using substrate bonding techniques 失效
    使用基板接合技术形成平面聚合物晶体管的方法

    公开(公告)号：US06620657B2

    公开(公告)日：2003-09-16

    申请号：US10052151

    申请日：2002-01-15

    申请人： Tricia L. Breen ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Kwong Hon Wong

    发明人： Tricia L. Breen ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Kwong Hon Wong

    IPC分类号： H01L2100

    CPC分类号： H01L51/0001 ,  H01L51/0024 ,  H01L51/0516 ,  H01L51/0541 ,  H01L51/0545

    摘要： A structure and method of forming a fully planarized polymer thin-film transistor by using a first planar carrier to process a first portion of the device including gate, source, drain and body elements. Preferably, the thin-film transistors made with all organic materials. The gate dielectric can be a high-k polymer to boost the device performance. Then, the partially-finished device structures are flipped upside-down and transferred to a second planar carrier. A layer of wax or photo-sensitive organic material is then applied, and can be used as the temporary glue. The device, including its body area, is then defined by an etching process. Contacts to the devices are formed by conductive material deposition and chemical-mechanical polish.

    摘要翻译： 通过使用第一平面载体来形成包括栅极，源极，漏极和主体元件的器件的第一部分来形成完全平坦化的聚合物薄膜晶体管的结构和方法。 优选地，由所有有机材料制成的薄膜晶体管。 栅极电介质可以是高k聚合物，以提高器件性能。 然后，部分完成的装置结构被颠倒翻转并转移到第二平面载体。 然后施加一层蜡或光敏有机材料，并且可以用作临时胶。 然后通过蚀刻工艺限定该装置，包括其身体区域。 与器件的接触通过导电材料沉积和化学机械抛光形成。

    Method and structure for providing improved thermal conduction for silicon semiconductor devices
    9.
    发明授权
    Method and structure for providing improved thermal conduction for silicon semiconductor devices 有权

    公开(公告)号：US06573565B2

    公开(公告)日：2003-06-03

    申请号：US09362399

    申请日：1999-07-28

    申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsomg-Dih Yuan

    发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsomg-Dih Yuan

    IPC分类号： H01L2362

    CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L23/3677 ,  H01L23/3732 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure. Yet another embodiment comprises diamond sidewalls formed along the device walls in thermal contact with the device junctions to provide heat dissipation through the device junctions to underlying cooling structures. It is also proposed that the foregoing structures, and combinations of the foregoing structures, could be used in conjunction with other known cooling schemes.