Chip scale package fabrication methods
    9.
    发明授权
    Chip scale package fabrication methods 有权
    芯片级封装制造方法

    公开(公告)号:US07745261B2

    公开(公告)日:2010-06-29

    申请号:US12109597

    申请日:2008-04-25

    申请人: Xiaochun Tan Jun Guo

    发明人: Xiaochun Tan Jun Guo

    IPC分类号: H01L21/00

    摘要: Embodiments of the present invention includes a method of assembling a chip scale package (CSP). The method comprises adding bumps, sawing the saw streets from the front of a wafer, molding the front of the wafer, grinding the back of the wafer, sawing the saw streets from the back of the wafer, molding the back of the wafer, and sawing between devices to form a plurality of packaged devices. Sawing the saw streets from the front of the wafer establishes a first cut. Molding the front of the wafer includes using a first mold compound such that the mold compound fills in the first cut. Sawing the saw streets from the back of the wafer establishes a second cut.

    摘要翻译: 本发明的实施例包括一种组装芯片级封装(CSP)的方法。 该方法包括添加凸块,从晶片的前面锯锯切街道,模制晶片的前部,研磨晶片的背面,从晶片的后面锯锯切街道,模制晶片的背面,以及 在设备之间切割以形成多个封装的装置。 从晶圆正面看锯街道,首先切割。 模制晶片的前部包括使用第一模具化合物,使得模具化合物填充在第一切割中。 从晶圆的背面锯锯道,建立了第二次切割。