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1.发明授权Semiconductor device including metal-insulator-metal capacitor arrangement 失效半导体器件包括金属 - 绝缘体 - 金属电容器布置公开(公告)号：US07705422B2
公开(公告)日：2010-04-27
申请号：US11247296
申请日：2005-10-12
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译： 半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。 第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。
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公开(公告)号：US20070262383A1
公开(公告)日：2007-11-15
申请号：US11767112
申请日：2007-06-22
IPC分类号： H01L31/0392
CPC分类号： H01L21/743 , H01L21/84 , H01L27/1203
摘要： A semiconductor IC device includes a base substrate comprising P−-type silicon, a first P+-type silicon layer is provided on the base substrate, and an N+-type silicon layer and a second P+-type silicon layer are provided in the same layer thereon. The impurity concentration of the first P+-type silicon layer and the N+-type silicon layer is higher than that of the base substrate. Also, a buried oxide layer and an SOI layer are provided on the entire upper surface of the N+-type silicon layer and the second P+-type silicon layer. The first P+-type silicon layer is connected to ground potential wiring GND, and the N+-type silicon layer is connected to power-supply potential wiring VDD. Accordingly, a decoupling capacitor, which is connected in parallel to the power supply, is formed between the P+-type silicon layer and the N+-type silicon layer.
摘要翻译： 半导体IC器件包括基底衬底，其包括P型 - 硅，第一P + +型硅层设置在基底衬底上，并且N + +型硅层和第二P + +型硅层设置在其上的同一层中。 第一P + + / - 型硅层和N + + - 型硅层的杂质浓度高于基底衬底的杂质浓度。 此外，在N + +型硅层和第二P + +型硅层的整个上表面上设置掩埋氧化物层和SOI层。 第一P + + / - 型硅层连接到地电位布线GND，并且N + +型硅层连接到电源电位布线VDD。 因此，在P + +型硅层和N + +型硅层之间形成与电源并联连接的去耦电容器。
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公开(公告)号：US20060237819A1
公开(公告)日：2006-10-26
申请号：US11407323
申请日：2006-04-20
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a capacitor with an MIM structure, by which the dimensional accuracy of the device is improved, and a stable capacitance value is given. The semiconductor device 100 includes: a semiconductor substrate 102; a capacitor forming region 130 in which an MIM capacitor is formed, which has an insulating interlayer 104 formed on the semiconductor substrate 102, a first electrode 110, and a second electrode 112, and the first electrode 110 and the second electrode 112 are arranged facing each other through the insulating interlayer 104; and a shielding region 132 which includes a plurality of shielding electrodes 114 formed in the outer edge of the capacitor forming region 130 and, at the same time, set at a predetermined potential in the same layer as that of the MIM capacitor on the semiconductor substrate 102, and shields the capacitor forming region 130 from other regions.
摘要翻译： 半导体器件包括具有MIM结构的电容器，通过该电容器提高器件的尺寸精度，并给出稳定的电容值。 半导体器件100包括：半导体衬底102; 形成有MIM电容器的电容器形成区域130，其具有形成在半导体衬底102上的绝缘中间层104，第一电极110和第二电极112，并且第一电极110和第二电极112面向 彼此通过绝缘夹层104; 以及屏蔽区域132，其包括形成在电容器形成区域130的外边缘中的多个屏蔽电极114，并且同时在与半导体衬底上的MIM电容器相同的层中设定预定电位 102，并且将电容器形成区域130与其他区域屏蔽。
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公开(公告)号：US20060180871A1
公开(公告)日：2006-08-17
申请号：US11338641
申请日：2006-01-25
申请人： Ryota Yamamoto , Kuniko Kikuta
发明人： Ryota Yamamoto , Kuniko Kikuta
IPC分类号： H01L29/76
CPC分类号： H01L21/823878 , H01L21/761 , H01L21/823892 , H01L27/0928
摘要： An N-type deep well is used to protect a circuit from a noise. However, a noise with a high frequency propagates through the N-type deep well, and as a result, the circuit that should be protected malfunctions. To reduce the area of the N-type deep well. For instance, in the present invention, a semiconductor device comprises a semiconductor substrate of a first conductivity type, a digital circuit part and an analog circuit part provided on the semiconductor substrate, a plurality of wells of the first conductivity type formed in either the analog circuit part or the digital circuit part, and a first deep well of a second conductivity type, which is the opposite conductivity type to the first conductivity type, isolating some of the plurality of wells from the semiconductor substrate.
摘要翻译： N型深井用于保护电路免受噪音。 然而，高频噪声通过N型深井传播，因此应保护的电路发生故障。 减少N型深井的面积。 例如，在本发明中，半导体器件包括第一导电类型的半导体衬底，设置在半导体衬底上的数字电路部分和模拟电路部分，第一导电类型的多个阱形成于模拟 电路部分或数字电路部分，以及与第一导电类型相反的导电类型的第二导电类型的第一深阱，从半导体衬底隔离多个阱中的一些。
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5.发明授权Semiconductor device including metal-insulator-metal capacitor arrangement 失效半导体器件包括金属 - 绝缘体 - 金属电容器布置公开(公告)号：US08378454B2
公开(公告)日：2013-02-19
申请号：US13173709
申请日：2011-06-30
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译： 半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。 第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。
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公开(公告)号：US07432170B2
公开(公告)日：2008-10-07
申请号：US11017695
申请日：2004-12-22
申请人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
发明人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.
摘要翻译： 在硅衬底上依次形成第一绝缘层，下导电层，电容器 - 绝缘体层和上导电层。 然后，形成第一抗蚀剂图案，蚀刻上导电层以形成上电极，并且在与上导电层的蚀刻条件相同的蚀刻条件下，电容器 - 绝缘体层被连续蚀刻。 接下来，形成第二抗蚀剂图案，蚀刻电容器 - 绝缘体层的其余部分以形成第二绝缘层，并且在与电容器 - 绝缘体层的蚀刻条件相同的蚀刻条件下，依次蚀刻下导电层，以便 形成下电极和下布线。 以这种方式，可以制造由上电极，第二绝缘层的一部分和下电极构成的MiM电容器元件。
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公开(公告)号：US07361845B2
公开(公告)日：2008-04-22
申请号：US10352301
申请日：2003-01-27
申请人： Ryota Yamamoto , Masayuki Furumiya
发明人： Ryota Yamamoto , Masayuki Furumiya
CPC分类号： H01L23/5227 , H01L2924/0002 , Y10T29/49155 , H01L2924/00
摘要： Wiring lines for use at a high frequency having reduced resistance and/or inductance are disclosed that may be readily manufactured in a semiconductor integrated circuit. Wiring lines can include extension lines (2), connected to both ends of an inductor (1), that may each include divided wiring lines (2a and 2b) that are separated by a slit (3). A length, width and thickness of divided wiring lines (2a and 2b) can be essentially equal, resulting in divided wiring lines (2a and 2b) of essentially equal longitudinal resistance. A width of a slit (3) may preferably be greater than a width of each of divided wiring lines (2a and 2b).
摘要翻译： 公开了可以容易地在半导体集成电路中制造的具有降低的电阻和/或电感的高频使用的布线。 连接线可以包括连接到电感器（2）的两端的延伸线（2），每条线可以包括被狭缝（3）分开的划分的布线（2a和2b）。 分开的布线（2a和2b）的长度，宽度和厚度可以基本上相等，导致基本相等的纵向电阻的分开的布线（2a和2b）。 狭缝（3）的宽度优选地可以大于分开的布线（2a和2b）的宽度。
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公开(公告)号：US20080048294A1
公开(公告)日：2008-02-28
申请号：US11892362
申请日：2007-08-22
申请人： Ryota Yamamoto
发明人： Ryota Yamamoto
CPC分类号： H01L23/585 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate; a circuit; a guard ring; a power source line; and a contact. The semiconductor substrate has a first conductive type. The circuit is formed on the semiconductor substrate. The guard ring is formed on the semiconductor substrate such that the guard ring surrounds the circuit. The power source line supplies an electric power both the circuit and the guard ring. The contact is formed on the guard ring and connects the guard ring and the power source line. The guard ring is composed of a semiconductor having a second conductive type opposite to the first conductive type. The contact is placed in an opposite side of a noise source over the circuit.
摘要翻译： 半导体器件包括半导体衬底; 电路 守卫环 电源线; 和联系人。 半导体衬底具有第一导电类型。 电路形成在半导体衬底上。 保护环形成在半导体基板上，使得保护环围绕电路。 电源线为电路和保护环提供电力。 触点形成在保护环上，并连接保护环和电源线。 保护环由具有与第一导电类型相反的第二导电类型的半导体构成。 触点放置在电路上的噪声源的相对侧。
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公开(公告)号：US07091576B2
公开(公告)日：2006-08-15
申请号：US10460306
申请日：2003-06-13
IPC分类号： H01L29/00
CPC分类号： H01L28/10 , H01L21/76838 , H01L23/5227 , H01L23/53228 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are an inductor for a semiconductor integrated circuit, which provides a wider cross-sectional area, significantly reduces the resistance to improve the Q value and has a highly uniform film thickness, and a method of fabricating the inductor. A spiral inductor is formed on a topmost interconnection layer of a multilayer interconnection layer formed by a damascene method. This inductor is formed by patterning a barrier metal layer on an insulation film, on which a topmost interconnection is formed, in such a way that the barrier metal layer contacts the topmost interconnection, then forming a protective insulation film on an entire surface of the barrier metal layer, forming an opening in that portion of the protective insulation film which lies over the barrier metal layer, forming a thick Cu film with the barrier metal layer serving as a plating electrode, and performing wet etching of the Cu film. This process can allow the inductor to be so formed as to be thick and have a wide line width.
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10.发明授权Solar cell sealing material and solar cell module produced using the same 有权太阳能电池密封材料和使用其制造的太阳能电池组件公开(公告)号：US08865835B2
公开(公告)日：2014-10-21
申请号：US13143803
申请日：2010-07-16
IPC分类号： H01L31/0203 , C09D153/00 , C08L53/00 , C08L23/04 , H01L31/048 , C08L23/08
CPC分类号： H01L31/048 , C08L23/0815 , C08L53/00 , C08L2203/204 , H01L31/0481 , Y02E10/50 , C08L2666/24
摘要： There is provided an encapsulant material for solar cells which facilitates production of a solar cell module and is excellent in flexibility, heat resistance, transparency, etc., and a solar cell module produced using the encapsulant material. The present invention relates to an encapsulant material for solar cells which includes a resin composition (C) containing an ethylene-α-olefin random copolymer (A) capable of satisfying the following condition (a) and an ethylene-α-olefin block copolymer (B) capable of satisfying the following condition (b): (a) a heat of crystal fusion is from 0 to 70 J/g as measured in differential scanning calorimetry at a heating rate of 10° C./min; and (b) a crystal fusion peak temperature is 100° C. or higher and a heat of crystal fusion is from 5 to 70 J/g as measured in differential scanning calorimetry at a heating rate of 10° C./min.
摘要翻译： 本发明提供一种太阳能电池用密封剂材料，该太阳能电池促进太阳能电池组件的制造，柔软性，耐热性，透明性等优异，以及使用该密封剂材料制造的太阳能电池组件。 本发明涉及一种太阳能电池用密封剂材料，其包含含有能够满足下述条件（a）的乙烯-α-烯烃无规共聚物（A）的树脂组合物（C）和乙烯-α-烯烃嵌段共聚物（ B）能够满足以下条件（b）：（a）在差示扫描量热法中以10℃/分钟的加热速率测量，结晶熔化热为0至70J / g; 和（b）以10℃/分钟的升温速度在差示扫描量热法中测定的结晶熔融峰温度为100℃以上，结晶熔融热为5〜70J / g。
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