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1.发明授权公开(公告)号：US11869444B2
公开(公告)日：2024-01-09
申请号：US17815590
申请日：2022-07-28
发明人： Chae Hee Park , Jong Soo Kim , Heen Dol Kim , Ji Ye Lee , Young Suk Jung
IPC分类号： G09G3/3275
CPC分类号： G09G3/3275 , G09G2310/0272 , G09G2310/08
摘要： A display device includes a timing controller for supplying a clock training signal through a data clock signal line in a first period of one frame period, and supplying image data through the data clock signal line in a second period of the one frame period, a data driver for generating a clock signal, based on the clock training signal in a clock training period in the first period, and generating a data signal, based on the clock signal and the image data in the second period, and a pixel unit for displaying an image, based on the data signal. The clock training signal includes a plurality of signal levels, and the data driver determines the clock training period, based on the signal levels of the clock training signal.
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公开(公告)号：US20230098067A1
公开(公告)日：2023-03-30
申请号：US17863791
申请日：2022-07-13
发明人： Heen Dol KIM , Jong Soo Kim , Chae Hee Park , Ji Ye Lee , Young Suk Jung
摘要： An embodiment of the present disclosure provides a data transmission method that transmits data in a clock-embedded manner, including: dividing the data into a plurality of data packets having a bit number of ‘a’; determining a transition code including information on a first transition facilitating data packet and a second transition facilitating data packet having the same high-order bits ([a−1:1]) among the data packets; converting the plurality of data packets into transition ensuring data packets by using the transition code; and transmitting the transition code and the transition ensuring data packets.
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公开(公告)号：US12125459B2
公开(公告)日：2024-10-22
申请号：US17863791
申请日：2022-07-13
发明人： Heen Dol Kim , Jong Soo Kim , Chae Hee Park , Ji Ye Lee , Young Suk Jung
CPC分类号： G09G5/008 , G06F13/4278 , G09G2370/10 , H03M5/06 , H04L7/0008 , H04L7/033 , H04L25/4906 , H04L25/493
摘要： An embodiment of the present disclosure provides a data transmission method that transmits data in a clock-embedded manner, including: dividing the data into a plurality of data packets having a bit number of ‘a’; determining a transition code including information on a first transition facilitating data packet and a second transition facilitating data packet having the same high-order bits ([a−1:1]) among the data packets; converting the plurality of data packets into transition ensuring data packets by using the transition code; and transmitting the transition code and the transition ensuring data packets.
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公开(公告)号：US11798495B2
公开(公告)日：2023-10-24
申请号：US17873365
申请日：2022-07-26
发明人： Chae Hee Park , Jong Soo Kim , Heen Dol Kim , Ji Ye Lee , Young Suk Jung
IPC分类号： G09G3/3291 , G09G3/3233
CPC分类号： G09G3/3291 , G09G3/3233 , G09G2300/0426 , G09G2300/0842 , G09G2310/08 , G09G2320/0626 , G09G2330/021 , G09G2330/026
摘要： A display device including: a timing controller configured to supply an adjustment option value through a data clock signal line during a first initialization period, and generate second data based on first data and a control signal and supply the second data through the data clock signal line during a data period; a data driver configured to generate an adjustment value based on the adjustment option value during the first initialization period, and generate third data based on the adjustment value and the second data and generate a data signal based on the third data during the data period; and a pixel configured to display an image based on the data signal.
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公开(公告)号：US11107385B2
公开(公告)日：2021-08-31
申请号：US16938329
申请日：2020-07-24
发明人： Soo Yeon Kim , Ji Ye Lee , Hee Jeong Seo , Tae Gon Im , Jung Hwan Cho
IPC分类号： G09G3/20
摘要： A display device includes a timing controller which supplies a clock training signal through a data clock signal line and a first control signal through a shared signal line in a first period of one frame, and supplies image data through the data clock signal line in a second period of the one frame, a data driver provided with data driving circuits which generate a clock signal based on the clock training signal and the first control signal in the first period, and generate data voltages based on the clock signal and the image data in the second period, and a pixel part which receives the data voltages from the data driver. The data driver may supply a second control signal indicating a reception state of the data driver to the timing controller through the shared signal line in the second period.
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公开(公告)号：US11799696B2
公开(公告)日：2023-10-24
申请号：US17866726
申请日：2022-07-18
发明人： Young Suk Jung , Weon Jun Choe , Heen Dol Kim , Chae Hee Park , Ji Ye Lee
CPC分类号： H04L25/0272 , H04B1/38 , H04L25/03
摘要： A transceiver of the present inventive concept includes a transmitter and a receiver connected by a first line and a second line, and the transmitter includes a first encoder; a second encoder; and a transmission driver. The first encoder generates a first encoded data different from a first data during a first period and the second encoder generates a second encoded data equal to a second data during the first period, the second encoder generates the second encoded data different from the second data during a second period and the first encoder generates the first encoded data equal to the first data during the second period, and the first period and the second period are arranged to alternate with each other.
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公开(公告)号：US10923010B2
公开(公告)日：2021-02-16
申请号：US16601469
申请日：2019-10-14
发明人： Won Tae Kim , Kyung Bae Kim , Ji Ye Lee
IPC分类号： G09G3/20
摘要： A display device includes a display panel including a first display region in which a plurality of first data lines are positioned and a second display region adjacent to the first display region in which a plurality of second data lines are positioned, a first data driver and a second data driver in a non-display region of the display panel, a plurality of first fan-out lines connected to the first data driver and including a plurality of 1_1-th fan-out lines connected to the plurality of first data lines and a plurality of 1_2-th fan-out lines connected to the plurality of second data lines, and a plurality of second fan-out lines connected to the second data driver and including a plurality of 2_1-th fan-out lines connected to the plurality of second data lines and a plurality of 2_2-th fan-out lines connected to the plurality of first data lines.
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