Thin film transistor display panel and method of manufacturing the same
    4.
    发明授权
    Thin film transistor display panel and method of manufacturing the same 有权
    薄膜晶体管显示面板及其制造方法

    公开(公告)号:US09147741B2

    公开(公告)日:2015-09-29

    申请号:US13892574

    申请日:2013-05-13

    CPC classification number: H01L29/4908 H01L29/518 H01L29/78603 H01L29/78633

    Abstract: A thin film transistor display panel according to an exemplary embodiment of the present invention includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed on the first insulating layer, a second insulating layer formed on the semiconductor layer, and a gate electrode formed on the second insulating layer, in which the first insulating layer includes a light blocking material, and a thickness of the first insulating layer is greater than or equal to a thickness of the second insulating layer.

    Abstract translation: 根据本发明的示例性实施例的薄膜晶体管显示面板包括基板,形成在基板上的第一绝缘层,形成在第一绝缘层上的半导体层,形成在半导体层上的第二绝缘层,以及 形成在第二绝缘层上的栅电极,其中第一绝缘层包括遮光材料,第一绝缘层的厚度大于或等于第二绝缘层的厚度。

    Organic light emitting diode display device

    公开(公告)号:US12075655B2

    公开(公告)日:2024-08-27

    申请号:US17151883

    申请日:2021-01-19

    CPC classification number: H10K59/1213 H10K59/1216 H10K59/123 H10K59/124

    Abstract: An organic light emitting diode display includes a first thin film transistor of which a channel is formed in a polycrystalline transistor, a second thin film transistor of which a channel is formed in an oxide semiconductor layer, an organic light emitting diode electrically connected to the first thin film transistor, a storage capacitor having a first electrode and a second electrode, wherein the second electrode of the storage capacitor is electrically connected to a gate electrode of the first thin film transistor, and an overlapping layer overlapping the oxide semiconductor layer in a plan view and receiving a positive voltage. The oxide semiconductor layer is positioned higher than the gate electrode of the first thin film transistor and the second electrode of the storage capacitor.

    Organic light emitting diode display

    公开(公告)号:US11616108B2

    公开(公告)日:2023-03-28

    申请号:US16661329

    申请日:2019-10-23

    Abstract: An organic light emitting diode display includes a substrate, an overlap layer on the substrate, a semiconductor layer on the overlap layer, a first gate conductor on the semiconductor layer, a second gate conductor on the first gate conductor, a data conductor on the second gate conductor, a driving transistor on the overlap layer, and an organic light emitting diode connected with the driving transistor. The driving transistor includes, in the semiconductor layer, a first electrode, a second electrode, with a channel therebetween. A gate electrode of the first gate conductor overlaps the channel. The overlap layer overlaps the channel of the driving transistor and at least a portion of the first electrode. A storage line of the second gate conductor receives a driving voltage through a driving voltage line in the data conductor. The overlap layer receives a constant voltage.

    Organic light emitting diode display device

    公开(公告)号:US10930725B2

    公开(公告)日:2021-02-23

    申请号:US16575643

    申请日:2019-09-19

    Abstract: An organic light emitting diode display includes a first thin film transistor of which a channel is formed in a polycrystalline transistor, a second thin film transistor of which a channel is formed in an oxide semiconductor layer, an organic light emitting diode electrically connected to the first thin film transistor, a storage capacitor having a first electrode and a second electrode, wherein the second electrode of the storage capacitor is electrically connected to a gate electrode of the first thin film transistor, and an overlapping layer overlapping the oxide semiconductor layer in a plan view and receiving a positive voltage. The oxide semiconductor layer is positioned higher than the gate electrode of the first thin film transistor and the second electrode of the storage capacitor.

    Display device and manufacturing method thereof

    公开(公告)号:US10826026B2

    公开(公告)日:2020-11-03

    申请号:US16203784

    申请日:2018-11-29

    Abstract: A method for manufacturing a display device including forming a lower electrode on a substrate; depositing a first insulation layer thereon; forming a semiconductor layer that overlaps the lower electrode thereon; depositing a second insulation layer thereon; forming a gate electrode and an etching prevention layer that overlap the semiconductor layer thereon; depositing a third insulation layer thereon; forming a first conductor that overlaps the gate electrode thereon; depositing a fourth insulation layer thereon; forming a photosensitive film patterns thereon by depositing a photosensitive film and exposing and developing the photosensitive film such that portions of the photosensitive film are removed in a first area, a second area, and a third area; etching the third insulation layer using the patterns as an etching mask; etching the etching prevention layer by using the patterns as an etching mask; and etching the first insulation layer using the patterns as an etching mask.

    Display device
    9.
    发明授权

    公开(公告)号:US10453911B2

    公开(公告)日:2019-10-22

    申请号:US15965160

    申请日:2018-04-27

    Abstract: A display device includes first semiconductor pattern including a first channel portion, a first electrode connected to a driving voltage line, and a second electrode connected to a light emitting element, a first insulating, a first conductive layer including a first gate electrode, a second insulating layer, a second conductive layer including an initialization power line, a third insulating layer, an upper semiconductor layer including a second semiconductor pattern including a second channel portion, a third electrode, and a fourth electrode connected to the first gate electrode, and a third semiconductor pattern including a third channel portion, a fifth electrode connected to the third electrode, and a sixth electrode connected to the second electrode, a fourth insulating layer, and a third conductive layer including a scan line and a control signal line, wherein the upper semiconductor layer does not overlap the first gate electrode and the initialization power line.

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