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    SEMICONDUCTOR DEVICES HAVING GATE ISOLATION LAYERS
    2.
    发明申请
    SEMICONDUCTOR DEVICES HAVING GATE ISOLATION LAYERS 有权

    公开(公告)号：US20220254880A1

    公开(公告)日：2022-08-11

    申请号：US17400358

    申请日：2021-08-12

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Seonbae KIM ,  Woojin LEE ,  Seunghoon CHOI

    IPC分类号： H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

    摘要： A semiconductor device includes active regions on a substrate, a gate structure intersecting the active regions, a source/drain region on the active regions and at a side surface of the gate structure, a gate spacer between the gate structure and the source/drain region, the gate spacer contacting the side surface of the gate structure, a lower source/drain contact plug connected to the source/drain region, a gate isolation layer on the gate spacer, an upper end of the gate isolation layer being at a higher level than an upper surface of the gate structure and an upper surface of the lower source/drain contact plug, a capping layer covering the gate structure, the lower source/drain contact plug, and the gate isolation layer, and an upper source/drain contact plug connected to the lower source/drain contact plug and extending through the capping layer.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200098620A1

    公开(公告)日：2020-03-26

    申请号：US16411439

    申请日：2019-05-14

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Woojin LEE ,  Hoon Seok SEO ,  Sanghoon AHN ,  Kyu-Hee HAN

    IPC分类号： H01L21/768 ,  H01L21/311

    摘要： A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

    INTEGRATED CIRCUIT DEVICE
    7.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20230129825A1

    公开(公告)日：2023-04-27

    申请号：US17828327

    申请日：2022-05-31

    申请人： Samsung Electronics Co., Ltd.

    发明人： Yeonggil KIM ,  Seonbae KIM ,  Woojin LEE ,  Jayeong HEO

    IPC分类号： H01L27/118

    摘要： An integrated circuit (IC) device including a fin-type active region on a substrate and a gate line on the fin-type active and having a first uppermost surface at a first vertical level, an insulating spacer covering a sidewall of the gate line and having a second uppermost surface at the first vertical level, and an insulating guide film covering the second uppermost surface of the insulating spacer may be provided. The gate line may include a multilayered conductive film structure that includes a plurality of conductive patterns and have a top surface defined by the conductive patterns, which includes at least first and second conductive patterns including different materials from each other and a unified conductive pattern that is in contact with a top surface of each of the conductive patterns and has a top surface that defines the first uppermost surface.

    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
    9.
    发明申请
    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210125856A1

    公开(公告)日：2021-04-29

    申请号：US16872955

    申请日：2020-05-12

    申请人： Samsung Electronics Co., Ltd.

    发明人： Sanghoon AHN ,  Woojin LEE ,  Kyuhee HAN

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

    摘要： An integrated circuit device according to the inventive concepts includes lower wiring structures formed on a substrate, an air gap arranged between the lower wiring structures, a capping layer covering an upper surface of the air gap, an etch stop layer conformally covering an upper surfaces of the lower wiring structures and the capping layer and having a protrusion and recess structure, an insulating layer covering the etch stop layer, and an upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered with the etch stop layer, wherein the upper wiring structure covers a portion of an upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structures.