公开(公告)号：US20240234253A1

公开(公告)日：2024-07-11

申请号：US18399173

申请日：2023-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wookyung YOU ,  Yeonggil KIM ,  Sangkoo KANG ,  Minjae KANG ,  Koungmin RYU ,  Hoonseok SEO ,  Woojin LEE

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L24/05 ,  H01L25/0657 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696 ,  H01L2224/0557 ,  H01L2225/06541 ,  H01L2924/13091

Abstract: A semiconductor device includes: a device structure including a first semiconductor substrate and having an active pattern extending in first direction, a conductive through-via electrically connected to a front wiring layer and penetrating through the first semiconductor substrate, wherein the first semiconductor substrate has a non-planarized lower surface in which a peripheral region around the conductive through-via curves downward, a first bonding structure having a planarized insulating layer disposed on the second surface of the first semiconductor substrate and having a planarized upper surface.

公开(公告)号：US20230129825A1

公开(公告)日：2023-04-27

申请号：US17828327

申请日：2022-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonggil KIM ,  Seonbae KIM ,  Woojin LEE ,  Jayeong HEO

IPC: H01L27/118

Abstract: An integrated circuit (IC) device including a fin-type active region on a substrate and a gate line on the fin-type active and having a first uppermost surface at a first vertical level, an insulating spacer covering a sidewall of the gate line and having a second uppermost surface at the first vertical level, and an insulating guide film covering the second uppermost surface of the insulating spacer may be provided. The gate line may include a multilayered conductive film structure that includes a plurality of conductive patterns and have a top surface defined by the conductive patterns, which includes at least first and second conductive patterns including different materials from each other and a unified conductive pattern that is in contact with a top surface of each of the conductive patterns and has a top surface that defines the first uppermost surface.

公开(公告)号：US20240421162A1

公开(公告)日：2024-12-19

申请号：US18529716

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minchul AHN ,  Yeonggil KIM ,  Sungbin PARK ,  Deokyoung JUNG

IPC: H01L27/12

Abstract: An integrated circuit device includes a backside insulating structure including an etch stop pattern, gate lines arranged over the backside insulating structure and each overlapping the etch stop pattern in a vertical direction, source/drain regions respectively arranged one-by-one between the gate lines, and a backside via contact passing through the etch stop pattern in the vertical direction and connected to a first source/drain region selected from the source/drain regions, wherein the backside via contact includes a stepped portion, which is apart from a first vertical level in the vertical direction by as much as a first distance and has a change in the width of the backside via contact in a horizontal direction at a second vertical level that is adjacent to the etch stop pattern, the first vertical level being closest to the plurality of gate lines in the backside insulating structure.

公开(公告)号：US20240258204A1

公开(公告)日：2024-08-01

申请号：US18486853

申请日：2023-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonggil KIM ,  Hoonseok SEO ,  Minchul AHN ,  Wookyung YOU ,  Woojin LEE ,  Junghwan CHUN

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device comprising: a substrate including an active region extending in a first direction; a gate structure extending in a second direction on the active region; source/drain regions on the active region and adjacent the gate structure; a backside insulating layer on a lower surface of the substrate; a vertical power structure between adjacent source/drain regions, wherein the vertical power structure extends through the substrate and the backside insulating layer and has an exposed lower surface exposed; an interlayer insulating layer on the backside insulating layer; a backside power structure that extends through the interlayer insulating layer and is connected to the vertical power structure; and a first alignment insulating layer between the backside insulating layer and the interlayer insulating layer, wherein the first alignment insulating layer has a first opening exposing the lower surface of the vertical power structure and contacts the backside power structure.

公开(公告)号：US20240145345A1

公开(公告)日：2024-05-02

申请号：US18209206

申请日：2023-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonggil KIM ,  Hoon Seok SEO ,  Yungbae KIM ,  Wookyung YOU

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes active patterns on a substrate, source/drain patterns, first and second separation structures, wherein adjacent source/drain patterns are interposed between the first and second separation structures, an interlayer insulating layer on the source/drain patterns and first and second separation structures, a through-via between the adjacent source/drain patterns, penetrating the interlayer insulating layer, and extending toward the substrate, wherein a top of the through-via is coplanar with a top of the interlayer insulating layer, a dielectric layer selectively on the top of the interlayer insulating layer, and opening the top of the through-via, a power via guided to connect to the top of the through-via by the dielectric layer, a power line on the power via and electrically connected to the through-via through the power via, a power delivery network layer on a bottom of the substrate, and a lower conductor under the through-via.