公开(公告)号：US10438998B2

公开(公告)日：2019-10-08

申请号：US15828937

申请日：2017-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Hongsoo Kim ,  Junhee Lim ,  Chang-Hoon Jeon

IPC: G11C5/02 ,  H01L27/24 ,  G11C11/00 ,  H01L45/00 ,  H01L27/11573 ,  G11C13/00 ,  H01L27/22 ,  G11C11/16 ,  H01L43/08 ,  H01L49/02 ,  H01L27/11582

Abstract: Integrated circuit devices may include a substrate including a flash memory region and a variable resistance memory region, a flash memory cell transistor including a cell gate electrode that overlaps the flash memory region of the substrate, a variable resistance element that overlaps the variable resistance memory region of the substrate, and a select transistor including a select source/drain region that is disposed in the variable resistance memory region of the substrate. The select source/drain region may be electrically connected to the variable resistance element. The substrate may include an upper surface facing the cell gate electrode and the variable resistance element, and the upper surface of the substrate may continuously extend from the flash memory region to the variable resistance memory region.

公开(公告)号：US20180358408A1

公开(公告)日：2018-12-13

申请号：US15828937

申请日：2017-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilho LEE ,  Gwanhyeob Koh ,  Hongsoo Kim ,  Junhee Lim ,  Chang-Hoon Jeon

IPC: H01L27/22 ,  G11C5/02 ,  G11C11/16 ,  H01L27/24 ,  H01L49/02 ,  H01L43/08

CPC classification number: H01L27/228 ,  G11C5/025 ,  G11C11/005 ,  G11C11/161 ,  G11C11/1659 ,  G11C13/0002 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/224 ,  H01L27/2436 ,  H01L27/2463 ,  H01L28/20 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233

Abstract: Integrated circuit devices may include a substrate including a flash memory region and a variable resistance memory region, a flash memory cell transistor including a cell gate electrode that overlaps the flash memory region of the substrate, a variable resistance element that overlaps the variable resistance memory region of the substrate, and a select transistor including a select source/drain region that is disposed in the variable resistance memory region of the substrate. The select source/drain region may be electrically connected to the variable resistance element. The substrate may include an upper surface facing the cell gate electrode and the variable resistance element, and the upper surface of the substrate may continuously extend from the flash memory region to the variable resistance memory region.