Abstract:
An integrated circuit (IC) system including a first substrate comprising passive components, a first power managing IC chip including a first power managing IC stacked on the first substrate, first IC chip group including a IC stacked on top of the first power managing IC chip, a control IC chip, stacked on top of the first IC group, including a control IC configured to control the first IC and a second IC of a second IC chip group, the second IC chip group including the second IC stacked on top of the control IC chip, a second power managing IC chip including a second power managing IC stacked on top of the second IC chip group, and a second substrate comprising passive components stacked on top of the second power managing IC chip.
Abstract:
An apparatus and method for tracking maximum power are disclosed. The apparatus is configured to track a maximum power at a certain node of an electronic circuit, adjust an impedance of the electronic circuit such that power at the node is maximal, and adjust an impedance of the electronic circuit by comparing power at two points in time to increase power. The apparatus for tracking a maximum power, includes a charge sharing capacitor connected to an initial capacitor in parallel, a first switch disposed between the initial capacitor and an energy harvesting power supply, a second switch disposed between the initial capacitor and the charge sharing capacitor, a third switch disposed between the energy harvesting power supply and a comparator, and a switched-capacitor power converting circuit configured to control the initial capacitor.
Abstract:
A method and apparatus for authenticating a user are provided. An authentication apparatus includes a data set generator configured to generate an authentication data set by extracting waveforms from a biosignal of a user, a similarity calculator configured to match each of the extracted waveforms to registered waveforms included in a registration data set, and calculate a similarity between each of the extracted waveforms and the registered waveforms, and an auxiliary similarity calculator configured to extract a representative authentication waveform indicating a representative waveform of the extracted waveforms and a representative registration waveform indicating a representative waveform of the registered waveforms, and calculate a similarity between the representative authentication waveform and the representative registration waveform.
Abstract:
A three-dimensional (3D) nanoprobe device includes a body portion including a plurality of body layers that are stacked, a plurality of nanoprobes respectively extending longitudinally from the body portion, with each of the plurality of nanoprobes comprising a plurality of extension layers that are stacked, and an electrode portion disposed on a portion of the body portion.
Abstract:
A multichannel apparatus for exchanging channels and an operating method of the multichannel apparatus are provided. The apparatus includes reception nodes configured to receive input signals of an analog domain, main signal processors configured to perform a signal processing operation on the input signals, and auxiliary signal processors configured to replace the main signal processors and perform at least a portion of the signal processing operation in response to a replacement condition being satisfied. The reception nodes, the main signal processors, and the auxiliary signal processors are implemented in a single integrated circuit (IC) package.
Abstract:
A method and apparatus of processing a signal, where the method may include receiving spike signals of neurons detected by each of a plurality of electrodes, grouping electrodes, from among the plurality of electrodes, corresponding to spike signals generated from a neuron of the neurons into a group, calculating weights corresponding to the grouped electrodes, and processing signals for each of the neurons based on the weights.
Abstract:
A method of controlling power on a low-power device and the low-power device for performing the method are provided. The method includes performing a first operation, of acquiring sensing data, using power stored in an internal battery of the low-power device, wherein the first operation consumes a first power consumption from the internal battery; and performing a second operation, with respect to the acquired sensing data, and which consumes a second power consumption, using power wirelessly transmitted from an external device located outside of the low-power device, wherein the second power consumption is greater than the first power consumption.
Abstract:
A method to update reference verification information used for electrocardiogram (ECG) signal verification includes: identifying a first ECG signal measured from a user; verifying the first ECG signal by comparing a second ECG signal included in a reference ECG signal set with the first ECG signal; in response to the first ECG signal being successfully verified, setting the successfully verified first ECG signal to be a third ECG signal, and adding the third ECG signal to a verified ECG signal set; and updating the reference ECG signal set by setting the third ECG signal added to the verified ECG signal set to be an additional second ECG signal, based on the reference ECG signal set and the verified ECG signal set.
Abstract:
A nanocavity-based electrode and a complementary metal-oxide-semiconductor-based device including the same are provided. In the nanocavity-based electrode, a single or a plurality of unit layers is stacked, and each unit layer includes a single or a plurality of nanocavities.
Abstract:
An integrated circuit having a plurality of stacked chips, and a method of manufacturing thereof are provided. The integrated circuit includes a substrate, a plurality of chips stacked on a printed circuit board, wherein each of the plurality of chips includes a plurality of circuits, and a plurality of interconnects configured to electrically connect each of the plurality of circuits included in the each of the plurality of chips to the substrate, wherein the plurality of chips are unconnected with regard to each other, and are stacked such that areas of each of the plurality of chips, to which the plurality of interconnects are connected, are disposed in a non-overlapping manner with each other.