公开(公告)号：US11302384B2

公开(公告)日：2022-04-12

申请号：US16931933

申请日：2020-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chulung Kim ,  Joungyeal Kim ,  Seongheon Yu ,  Hyunjin Ko ,  Wooil Kim ,  Hyeonsoo Sim

IPC: G11C11/4093 ,  G11C11/4096 ,  G06F13/40 ,  G06F13/16 ,  H01L25/065 ,  H01L25/18

Abstract: In a method of controlling on-die termination (ODT) in a memory system including a plurality of memory units that shares a data bus to transfer data, ODT circuits of the plurality of memory units are enabled into an initial state, a resistance value of the ODT circuit is set to a first resistance value, of at least one write non-target memory unit among the plurality of memory units during a write operation on a write target memory unit among the plurality of memory units, and a resistance value of the ODT circuit is set to a second resistance value, of at least one read non-target memory unit among the plurality of memory units during a read operation on a read target memory unit among the plurality of memory units.

公开(公告)号：US11923042B2

公开(公告)日：2024-03-05

申请号：US17581445

申请日：2022-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwoo Kim ,  Younghoon Son ,  Seongheon Yu ,  Joungyeal Kim ,  Chulung Kim

IPC: G11C7/22 ,  G11C7/10 ,  G11C29/12 ,  G11C29/46

CPC classification number: G11C7/222 ,  G11C7/1069 ,  G11C7/1096 ,  G11C29/12015 ,  G11C29/46

Abstract: An apparatus includes a host and a memory device connected to the host through a bus. The bus is used to communicate a data clock controlling data write timing during a write operation executed by the memory device and a read clock controlling data read timing during a read operation executed by the memory device. The memory device performs first duty cycle monitoring that monitors a duty cycle of the data clock, generates a first result, and provides a timing-adjusted data clock, performs second duty cycle monitoring that monitors a duty cycle of the read clock, generates a second result, and provides a timing-adjusted read clock, calculates an offset of the read clock based on the timing-adjusted data clock, the result and the second result, and corrects a duty error of the read clock using a read clock offset code derived from the offset of the read clock.