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公开(公告)号:US20240312959A1
公开(公告)日:2024-09-19
申请号:US18675679
申请日:2024-05-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: DOOHWAN LEE , JUNGSOO BYUN
IPC: H01L25/065 , H01L23/00 , H01L23/04 , H01L23/31 , H01L23/538
CPC classification number: H01L25/0657 , H01L23/041 , H01L23/3128 , H01L23/5383 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L2224/0401 , H01L2224/16227 , H01L2224/1703 , H01L2224/32145 , H01L2224/73203 , H01L2225/06562
Abstract: A semiconductor package includes a frame having a through-opening, a first semiconductor chip disposed in the through-opening and having a first active surface on which a first connection pad is disposed and a first inactive surface opposing the first active surface, a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second inactive surface opposing the second active surface, first and second bumps electrically connected to the first and second connection pads, respectively, first and second dummy bumps disposed on a same level as levels of the first and second bumps, respectively, first and second posts electrically connected to the first and second bumps, respectively, a connection member including a redistribution layer electrically connected to each of the first and second posts, and a dummy post disposed between the frame and the connection member.
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公开(公告)号:US20230142938A1
公开(公告)日:2023-05-11
申请号:US17901386
申请日:2022-09-01
Applicant: Samsung Electronics Co., Ltd.
Inventor: JINGU KIM , DOOHWAN LEE , SANGKYU LEE , JEONGHO LEE , TAESUNG JEONG
IPC: H01L49/02 , H01L23/498 , H01L25/18 , H01L23/538
CPC classification number: H01L28/84 , H01L23/49822 , H01L23/49827 , H01L23/49816 , H01L25/18 , H01L23/5385 , H01L23/5383 , H01L23/5384 , H01L2224/16227 , H01L2224/16145 , H01L24/16
Abstract: A semiconductor device includes a substrate having a recess region, a first electrode in the recess region and having a three-dimensional network structure, a first dielectric layer in the recess region and covering the first electrode, a second electrode in the recess region and covering the first dielectric layer, and a molding layer filling a remaining portion of the recess region and covering the second electrode.
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公开(公告)号:US20220181303A1
公开(公告)日:2022-06-09
申请号:US17679861
申请日:2022-02-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: DOOHWAN LEE , JUNGSOO BYUN
IPC: H01L25/065 , H01L23/04 , H01L23/00 , H01L23/538 , H01L23/31
Abstract: A semiconductor package includes a frame having a through-opening, a first semiconductor chip disposed in the through-opening and having a first active surface on which a first connection pad is disposed and a first inactive surface opposing the first active surface, a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second inactive surface opposing the second active surface, first and second bumps electrically connected to the first and second connection pads, respectively, first and second dummy bumps disposed on a same level as levels of the first and second bumps, respectively, first and second posts electrically connected to the first and second bumps, respectively, a connection member including a redistribution layer electrically connected to each of the first and second posts, and a dummy post disposed between the frame and the connection member.
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公开(公告)号:US20230115073A1
公开(公告)日:2023-04-13
申请号:US17815634
申请日:2022-07-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: SANGKYU LEE , DOOHWAN LEE
IPC: H01L23/538 , H01L25/065 , H01L23/00 , H01L23/498 , H01L23/48
Abstract: A semiconductor package includes a frame having a first surface and a second surface, and including a wiring structure and a through-hole. The package further includes a first redistribution structure disposed on the first surface of the frame and including a first insulating layer and a first redistribution layer on the first insulating layer and connected to the wiring structure, a bridge die in the through-hole and having an interconnector, and an encapsulant surrounding the bridge die, and covering the second surface of the frame. The package further includes a second redistribution structure disposed on the encapsulant, and including a second insulating layer and a second redistribution layer on the second insulating layer and connected to the interconnector and the wiring structure, and a plurality of semiconductor chips disposed on the second redistribution structure, connected to the second redistribution layer, and electrically connected to each other through the interconnector.
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公开(公告)号:US20220310577A1
公开(公告)日:2022-09-29
申请号:US17501108
申请日:2021-10-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: DOOHWAN LEE , SEOKHYUN LEE , JEONGHO LEE
IPC: H01L25/18 , H01L23/538 , H01L23/498 , H01L25/065
Abstract: A semiconductor package may include a first redistribution layer, a passive device disposed on a top surface of the first redistribution layer, a bridge structure disposed on the top surface of the first redistribution layer and laterally spaced apart from the passive device, a second redistribution layer disposed on and electrically connected to the passive device and the bridge structure, conductive structures disposed between the first redistribution layer and the second redistribution layer and laterally spaced apart from the passive device and the bridge structure, a first semiconductor chip mounted on a top surface of the second redistribution layer, and a second semiconductor chip mounted on the top surface of the second redistribution layer. The conductive structures may include a signal structure and a ground/power structure, which is laterally spaced apart from the signal structure and has a width larger than the signal structure.
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公开(公告)号:US20220262777A1
公开(公告)日:2022-08-18
申请号:US17511178
申请日:2021-10-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: DOOHWAN LEE , Wonkyoung CHOI , JEONGHO LEE
IPC: H01L25/10 , H01L23/00 , H01L23/498
Abstract: A semiconductor package includes a first substrate, a first semiconductor chip and a passive device which are laterally spaced apart from each other on the first substrate and are disposed face-up on the first substrate, a first molding part surrounding the first semiconductor chip and the passive device on the first substrate, a second semiconductor chip disposed on the first molding part and electrically connected to the first semiconductor chip and the passive device, a second molding part surrounding the second semiconductor chip on the first molding part, first through-electrodes vertically penetrating the first molding part, at least some of first through-electrodes electrically connect the first substrate to the second semiconductor chip, and external terminals provided under the first substrate.
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