公开(公告)号：US20230143267A1

公开(公告)日：2023-05-11

申请号：US17895260

申请日：2022-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAEHO SHIN ,  JEONGHO LEE ,  YOUNGGEON YOO ,  HYEOKJUN CHOE

IPC: G06F12/02 ,  G06F12/14 ,  H04L9/08

CPC classification number: G06F12/02 ,  G06F12/14 ,  H04L9/0825

Abstract: In a method of allocating and protecting a memory in a computational storage device including a first computing engine and a buffer memory, a memory allocation request is received from a host device that is disposed outside the computational storage device. Based on the memory allocation request, a memory allocation operation in which a first memory region is generated in the buffer memory and a first key associated with the first memory region is generated is performed. A program execution request is received from the host device. Based on the program execution request, a program execution operation is performed in which a first program is executed by the first computing engine by accessing the first memory region based on an encryption or a decryption using the first key.

公开(公告)号：US20230142938A1

公开(公告)日：2023-05-11

申请号：US17901386

申请日：2022-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINGU KIM ,  DOOHWAN LEE ,  SANGKYU LEE ,  JEONGHO LEE ,  TAESUNG JEONG

IPC: H01L49/02 ,  H01L23/498 ,  H01L25/18 ,  H01L23/538

CPC classification number: H01L28/84 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49816 ,  H01L25/18 ,  H01L23/5385 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2224/16227 ,  H01L2224/16145 ,  H01L24/16

Abstract: A semiconductor device includes a substrate having a recess region, a first electrode in the recess region and having a three-dimensional network structure, a first dielectric layer in the recess region and covering the first electrode, a second electrode in the recess region and covering the first dielectric layer, and a molding layer filling a remaining portion of the recess region and covering the second electrode.

公开(公告)号：US20230052799A1

公开(公告)日：2023-02-16

申请号：US17972804

申请日：2022-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20220027232A1

公开(公告)日：2022-01-27

申请号：US17495632

申请日：2021-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE ,  YENA LEE

IPC: G06F11/10 ,  G06F11/30 ,  G06F9/54 ,  G11C13/00 ,  G06F12/02 ,  G06F9/30

Abstract: An operating method of a memory device, which includes a first memory region and a second memory region, includes reading first data from the first memory region and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and second data read from the second memory region to generate first result data, writing the first data stored in the data buffer block in the second memory region, performing a second XOR operation on the first data and the first result data to generate the second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block in the first memory region.

公开(公告)号：US20200341843A1

公开(公告)日：2020-10-29

申请号：US16840581

申请日：2020-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20220352097A1

公开(公告)日：2022-11-03

申请号：US17867388

申请日：2022-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINGU KIM ,  SHANGHOON SEO ,  SANGKYU LEE ,  JEONGHO LEE

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package includes: a frame substrate having a plurality of wiring layers and a cavity; an adhesive member disposed at the bottom of the cavity; a semiconductor chip disposed in the cavity, with a connection pad on an upper surface and the lower surface in contact with the adhesive member; a first conductive bump disposed on the connection pad; a second conductive bump disposed on the uppermost of the plurality of wiring layers; an insulating post disposed in the cavity and whose lower surface contacts the adhesive member; an encapsulant filling the cavity and covering side surfaces of the first and second conductive bumps and the insulating post' and a redistribution structure disposed on the encapsulant, including a redistribution layer electrically connected to the first and second conductive bumps, wherein the insulating post includes a material having a greater hardness than that of the first and second conductive bumps.

公开(公告)号：US20220310577A1

公开(公告)日：2022-09-29

申请号：US17501108

申请日：2021-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： DOOHWAN LEE ,  SEOKHYUN LEE ,  JEONGHO LEE

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package may include a first redistribution layer, a passive device disposed on a top surface of the first redistribution layer, a bridge structure disposed on the top surface of the first redistribution layer and laterally spaced apart from the passive device, a second redistribution layer disposed on and electrically connected to the passive device and the bridge structure, conductive structures disposed between the first redistribution layer and the second redistribution layer and laterally spaced apart from the passive device and the bridge structure, a first semiconductor chip mounted on a top surface of the second redistribution layer, and a second semiconductor chip mounted on the top surface of the second redistribution layer. The conductive structures may include a signal structure and a ground/power structure, which is laterally spaced apart from the signal structure and has a width larger than the signal structure.

公开(公告)号：US20220262777A1

公开(公告)日：2022-08-18

申请号：US17511178

申请日：2021-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： DOOHWAN LEE ,  Wonkyoung CHOI ,  JEONGHO LEE

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package includes a first substrate, a first semiconductor chip and a passive device which are laterally spaced apart from each other on the first substrate and are disposed face-up on the first substrate, a first molding part surrounding the first semiconductor chip and the passive device on the first substrate, a second semiconductor chip disposed on the first molding part and electrically connected to the first semiconductor chip and the passive device, a second molding part surrounding the second semiconductor chip on the first molding part, first through-electrodes vertically penetrating the first molding part, at least some of first through-electrodes electrically connect the first substrate to the second semiconductor chip, and external terminals provided under the first substrate.

公开(公告)号：US20220012128A1

公开(公告)日：2022-01-13

申请号：US17448995

申请日：2021-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20210272913A1

公开(公告)日：2021-09-02

申请号：US17016123

申请日：2020-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINGU KIM ,  SHANGHOON SEO ,  SANGKYU LEE ,  JEONGHO LEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes: a frame substrate having a plurality of wiring layers and a cavity; an adhesive member disposed at the bottom of the cavity; a semiconductor chip disposed in the cavity, with a connection pad on an upper surface and the lower surface in contact with the adhesive member; a first conductive bump disposed on the connection pad; a second conductive bump disposed on the uppermost of the plurality of wiring layers; an insulating post disposed in the cavity and whose lower surface contacts the adhesive member; an encapsulant filling the cavity and covering side surfaces of the first and second conductive bumps and the insulating post’ and a redistribution structure disposed on the encapsulant, including a redistribution layer electrically connected to the first and second conductive bumps, wherein the insulating post includes a material having a greater hardness than that of the first and second conductive bumps.