公开(公告)号：US20240258277A1

公开(公告)日：2024-08-01

申请号：US18457504

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YI EOK KWON ,  JINGU KIM ,  SANGKYU LEE

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L24/06 ,  H01L25/18 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80006 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0544 ,  H10B80/00

Abstract: A semiconductor package includes: a front side redistribution layer; a three-dimensional integrated circuit (3D IC) structure on the front side redistribution layer, the 3D IC structure including a first semiconductor chip die having through-silicon vias (TSVs) and a second semiconductor chip die disposed on the first semiconductor chip die, and the second semiconductor chip die being electrically coupled with the front side redistribution layer by the through-silicon vias (TSVs); a plurality of connection members between the first semiconductor chip die and the second semiconductor chip die; an insulating member disposed between the first semiconductor chip die and the second semiconductor chip die to surround the plurality of connection members; a molding material disposed on the front side redistribution layer to encapsulate the first semiconductor chip die, the second semiconductor chip die, and the insulating member; and a back side redistribution layer disposed on the molding material.

公开(公告)号：US20230142938A1

公开(公告)日：2023-05-11

申请号：US17901386

申请日：2022-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINGU KIM ,  DOOHWAN LEE ,  SANGKYU LEE ,  JEONGHO LEE ,  TAESUNG JEONG

IPC: H01L49/02 ,  H01L23/498 ,  H01L25/18 ,  H01L23/538

CPC classification number: H01L28/84 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49816 ,  H01L25/18 ,  H01L23/5385 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2224/16227 ,  H01L2224/16145 ,  H01L24/16

Abstract: A semiconductor device includes a substrate having a recess region, a first electrode in the recess region and having a three-dimensional network structure, a first dielectric layer in the recess region and covering the first electrode, a second electrode in the recess region and covering the first dielectric layer, and a molding layer filling a remaining portion of the recess region and covering the second electrode.

公开(公告)号：US20220352097A1

公开(公告)日：2022-11-03

申请号：US17867388

申请日：2022-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINGU KIM ,  SHANGHOON SEO ,  SANGKYU LEE ,  JEONGHO LEE

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package includes: a frame substrate having a plurality of wiring layers and a cavity; an adhesive member disposed at the bottom of the cavity; a semiconductor chip disposed in the cavity, with a connection pad on an upper surface and the lower surface in contact with the adhesive member; a first conductive bump disposed on the connection pad; a second conductive bump disposed on the uppermost of the plurality of wiring layers; an insulating post disposed in the cavity and whose lower surface contacts the adhesive member; an encapsulant filling the cavity and covering side surfaces of the first and second conductive bumps and the insulating post' and a redistribution structure disposed on the encapsulant, including a redistribution layer electrically connected to the first and second conductive bumps, wherein the insulating post includes a material having a greater hardness than that of the first and second conductive bumps.

公开(公告)号：US20210272913A1

公开(公告)日：2021-09-02

申请号：US17016123

申请日：2020-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINGU KIM ,  SHANGHOON SEO ,  SANGKYU LEE ,  JEONGHO LEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes: a frame substrate having a plurality of wiring layers and a cavity; an adhesive member disposed at the bottom of the cavity; a semiconductor chip disposed in the cavity, with a connection pad on an upper surface and the lower surface in contact with the adhesive member; a first conductive bump disposed on the connection pad; a second conductive bump disposed on the uppermost of the plurality of wiring layers; an insulating post disposed in the cavity and whose lower surface contacts the adhesive member; an encapsulant filling the cavity and covering side surfaces of the first and second conductive bumps and the insulating post’ and a redistribution structure disposed on the encapsulant, including a redistribution layer electrically connected to the first and second conductive bumps, wherein the insulating post includes a material having a greater hardness than that of the first and second conductive bumps.