公开(公告)号：US20240258277A1

公开(公告)日：2024-08-01

申请号：US18457504

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YI EOK KWON ,  JINGU KIM ,  SANGKYU LEE

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L24/06 ,  H01L25/18 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80006 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0544 ,  H10B80/00

Abstract: A semiconductor package includes: a front side redistribution layer; a three-dimensional integrated circuit (3D IC) structure on the front side redistribution layer, the 3D IC structure including a first semiconductor chip die having through-silicon vias (TSVs) and a second semiconductor chip die disposed on the first semiconductor chip die, and the second semiconductor chip die being electrically coupled with the front side redistribution layer by the through-silicon vias (TSVs); a plurality of connection members between the first semiconductor chip die and the second semiconductor chip die; an insulating member disposed between the first semiconductor chip die and the second semiconductor chip die to surround the plurality of connection members; a molding material disposed on the front side redistribution layer to encapsulate the first semiconductor chip die, the second semiconductor chip die, and the insulating member; and a back side redistribution layer disposed on the molding material.

公开(公告)号：US20230142938A1

公开(公告)日：2023-05-11

申请号：US17901386

申请日：2022-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINGU KIM ,  DOOHWAN LEE ,  SANGKYU LEE ,  JEONGHO LEE ,  TAESUNG JEONG

IPC: H01L49/02 ,  H01L23/498 ,  H01L25/18 ,  H01L23/538

CPC classification number: H01L28/84 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49816 ,  H01L25/18 ,  H01L23/5385 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2224/16227 ,  H01L2224/16145 ,  H01L24/16

Abstract: A semiconductor device includes a substrate having a recess region, a first electrode in the recess region and having a three-dimensional network structure, a first dielectric layer in the recess region and covering the first electrode, a second electrode in the recess region and covering the first dielectric layer, and a molding layer filling a remaining portion of the recess region and covering the second electrode.

公开(公告)号：US20230230943A1

公开(公告)日：2023-07-20

申请号：US18125989

申请日：2023-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkoon Lee ,  Jingu Kim ,  SANGKYU LEE ,  Seokkyu Choi

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01Q9/04 ,  H01Q19/00 ,  H01L23/31

CPC classification number: H01L23/66 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/20 ,  H01L21/6835 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L24/19 ,  H01Q9/0407 ,  H01Q19/005 ,  H01L23/3121 ,  H01L2221/68372 ,  H01L2223/6677 ,  H01L2224/214

Abstract: A semiconductor package includes a supporting wiring structure including a first redistribution dielectric layer and a first redistribution conductive structure; a frame on the supporting wiring structure, having a mounting space and a through hole, and including a conductive material; a semiconductor chip in the mounting space and electrically connected to the first redistribution conductive structure; a cover wiring structure on the frame and the semiconductor chip and including a second redistribution dielectric layer and a second redistribution conductive structure; an antenna structure on the cover wiring structure; a connection structure extending in the through hole and electrically connecting the first redistribution conductive structure to the second redistribution conductive structure; and a dielectric filling member between the connection structure in the through hole and the frame and surrounding the semiconductor chip, the frame, and the connection structure.

公开(公告)号：US20230115073A1

公开(公告)日：2023-04-13

申请号：US17815634

申请日：2022-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGKYU LEE ,  DOOHWAN LEE

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/48

Abstract: A semiconductor package includes a frame having a first surface and a second surface, and including a wiring structure and a through-hole. The package further includes a first redistribution structure disposed on the first surface of the frame and including a first insulating layer and a first redistribution layer on the first insulating layer and connected to the wiring structure, a bridge die in the through-hole and having an interconnector, and an encapsulant surrounding the bridge die, and covering the second surface of the frame. The package further includes a second redistribution structure disposed on the encapsulant, and including a second insulating layer and a second redistribution layer on the second insulating layer and connected to the interconnector and the wiring structure, and a plurality of semiconductor chips disposed on the second redistribution structure, connected to the second redistribution layer, and electrically connected to each other through the interconnector.

公开(公告)号：US20230223309A1

公开(公告)日：2023-07-13

申请号：US17953092

申请日：2022-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEHOON JANG ,  SANGKYU LEE

IPC: H01L23/29 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/295 ,  H01L21/56 ,  H01L21/4857 ,  H01L23/293 ,  H01L21/4853 ,  H01L2224/73204 ,  H01L24/73

Abstract: A method of manufacture for a semiconductor package includes; forming a first wiring structure, connecting a semiconductor chip to the first wiring structure, forming a lower encapsulant on the first wiring structure to cover at least a portion of a lateral surface of the semiconductor chip, wherein the lower encapsulant does not cover an upper surface of the semiconductor chip, forming an upper encapsulant on the lower encapsulant, wherein the upper encapsulant covers the upper surface of the semiconductor chip and the upper encapsulant has a materially different composition than the lower encapsulant, and forming a second wiring structure on the upper encapsulant.

公开(公告)号：US20220352097A1

公开(公告)日：2022-11-03

申请号：US17867388

申请日：2022-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINGU KIM ,  SHANGHOON SEO ,  SANGKYU LEE ,  JEONGHO LEE

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package includes: a frame substrate having a plurality of wiring layers and a cavity; an adhesive member disposed at the bottom of the cavity; a semiconductor chip disposed in the cavity, with a connection pad on an upper surface and the lower surface in contact with the adhesive member; a first conductive bump disposed on the connection pad; a second conductive bump disposed on the uppermost of the plurality of wiring layers; an insulating post disposed in the cavity and whose lower surface contacts the adhesive member; an encapsulant filling the cavity and covering side surfaces of the first and second conductive bumps and the insulating post' and a redistribution structure disposed on the encapsulant, including a redistribution layer electrically connected to the first and second conductive bumps, wherein the insulating post includes a material having a greater hardness than that of the first and second conductive bumps.

公开(公告)号：US20210272913A1

公开(公告)日：2021-09-02

申请号：US17016123

申请日：2020-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINGU KIM ,  SHANGHOON SEO ,  SANGKYU LEE ,  JEONGHO LEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes: a frame substrate having a plurality of wiring layers and a cavity; an adhesive member disposed at the bottom of the cavity; a semiconductor chip disposed in the cavity, with a connection pad on an upper surface and the lower surface in contact with the adhesive member; a first conductive bump disposed on the connection pad; a second conductive bump disposed on the uppermost of the plurality of wiring layers; an insulating post disposed in the cavity and whose lower surface contacts the adhesive member; an encapsulant filling the cavity and covering side surfaces of the first and second conductive bumps and the insulating post’ and a redistribution structure disposed on the encapsulant, including a redistribution layer electrically connected to the first and second conductive bumps, wherein the insulating post includes a material having a greater hardness than that of the first and second conductive bumps.