公开(公告)号：US20170358573A1

公开(公告)日：2017-12-14

申请号：US15687929

申请日：2017-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Young LEE ,  Sang-Hyun LEE ,  Myung-Hoon JUNG ,  Do-Hyoung KIM

IPC: H01L27/088 ,  H01L29/45 ,  H01L21/768 ,  H01L29/417 ,  H01L21/28 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/28114 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/78

Abstract: A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate pattern having a second height, an insulating pattern on the substrate covering the first and second gate patterns, the insulating pattern including a trench exposing the substrate between the first and second gate patterns, a spacer contacting at least a portion of a sidewall of the insulating pattern within the trench, the spacer spaced apart from the first and second gate patterns and having a third height larger than the first and second heights, and a contact structure filling the trench.

公开(公告)号：US20140057427A1

公开(公告)日：2014-02-27

申请号：US14070935

申请日：2013-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Kwon KIM ,  Young-Ju PARK ,  Dong-Hyuk YEAM ,  Yoo-jung LEE ,  Myeong-cheol KIM ,  Do-Hyoung KIM ,  Heung-Sik PARK

IPC: H01L21/28

CPC classification number: H01L21/28132 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656

Abstract: Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses.

Abstract translation: 示例性实施例涉及用于制造半导体器件的方法，其中可以在金属栅电极的下部中形成其中的金属栅极电极，而不产生空隙。 该方法可以包括提供衬底，在衬底上形成虚拟栅电极，在衬底上形成与虚拟栅电极相邻的栅极间隔物，通过同时去除虚拟栅电极的一部分形成第一凹槽， 所述第一凹部具有比下端更宽的上端，通过去除在形成所述第一凹部之后残留的所述虚设栅电极形成第二凹槽，以及通过沉积金属以填充所述第一凹部而形成金属栅电极，以填充所述第一凹部 第二个凹槽

公开(公告)号：US20160005615A1

公开(公告)日：2016-01-07

申请号：US14705969

申请日：2015-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do-Haing LEE ,  IL-SUP KIM ,  Do-Hyoung KIM ,  Woo-Cheol LEE ,  Hyun-Ho JUNG

IPC: H01L21/308 ,  H01L21/768

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/76816

Abstract: A method of forming patterns of a semiconductor device includes forming a material film on a substrate, forming a hard mask on the material film, forming a first mold mask pattern and a second mold mask pattern on the hard mask, forming a pair of first spacers to cover opposite sidewalls of the first mold mask pattern, and a pair of second spacers to cover opposite sidewalls of the second mold mask pattern, forming a first gap and a second gap to expose the hard mask by removing the first mold mask pattern and the second mold mask pattern, the first gap being formed between the pair of first spacers and the second gap being formed between the pair of second spacers, forming a mask pattern on the hard mask to cover the first gap and expose the second gap, forming an auxiliary pattern to cover the second gap, removing the mask pattern; and forming a hard mask pattern by patterning the hard mask using the first spacers, the second spacers and the auxiliary pattern as a mask.

Abstract translation: 一种形成半导体器件的图案的方法包括：在基片上形成材料膜，在所述材料膜上形成硬掩模，在所述硬掩模上形成第一模具掩模图案和第二模具掩模图案，形成一对第一间隔物 以覆盖第一模具掩模图案的相对侧壁，以及一对第二间隔件，以覆盖第二模具掩模图案的相对的侧壁，形成第一间隙和第二间隙以通过去除第一模具掩模图案以暴露硬掩模，并且 第二模具掩模图案，所述第一间隙形成在所述一对第一间隔件和所述第二间隙之间，形成在所述一对第二间隔件之间，在所述硬掩模上形成掩模图案以覆盖所述第一间隙并暴露所述第二间隙， 辅助图案覆盖第二间隙，去除掩模图案; 以及通过使用第一间隔物，第二间隔物和辅助图案作为掩模来图案化硬掩模来形成硬掩模图案。

公开(公告)号：US20170040221A1

公开(公告)日：2017-02-09

申请号：US15196870

申请日：2016-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol KIM ,  Dong-Hoon KHANG ,  Do-Hyoung KIM ,  Seung-Jin MUN ,  Yong-Joon CHOI ,  Seung-Mo HA

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/033 ,  H01L21/308 ,  H01L21/027 ,  H01L21/3115

CPC classification number: H01L21/823431 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/0273 ,  H01L21/0275 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31155 ,  H01L29/66795

Abstract: Methods for fabricating a semiconductor device include forming a composite film, forming a rough pattern on the composite film, forming a smooth pattern by subjecting the rough pattern to ion implantation and a plasma treatment, and patterning the composite film using the smooth pattern as a first mask.

Abstract translation: 制造半导体器件的方法包括在复合膜上形成复合膜，形成粗糙图案，通过使粗糙图案经受离子注入和等离子体处理形成平滑图案，并使用平滑图案将复合膜图案化为第一 面具。

公开(公告)号：US20150076616A1

公开(公告)日：2015-03-19

申请号：US14553665

申请日：2014-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo-Yeon JEONG ,  Myeong-Cheol KIM ,  Do-Hyoung KIM ,  Do-Haing LEE ,  Nam-Myun CHO ,  In-Ho KIM

IPC: H01L27/088 ,  H01L29/45

CPC classification number: H01L27/088 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern.

Abstract translation: 一种制造半导体器件的方法包括通过基板上的第一绝缘中间层形成栅极结构，使得栅极结构在其侧壁上包括间隔物，在栅极结构上形成第一硬掩模，使用 所述第一硬掩模作为蚀刻掩模以形成第一接触孔，使得所述第一接触孔暴露所述基板的顶表面，在所述基板的由所述第一接触孔暴露的所述顶表面上形成金属硅化物图案，并形成 插头电连接到金属硅化物图案。