公开(公告)号：US20180175109A1

公开(公告)日：2018-06-21

申请号：US15796919

申请日：2017-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-jin CHOI ,  Jung-ik OH ,  Bok-yeon WON ,  Gwang-hyun BAEK

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L27/2463 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/35 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/126 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/148

Abstract: A variable resistance memory device including a first electrode line; a cell structure including a variable resistance layer on the first electrode line and a first blocking layer protecting the variable resistance layer; and a second electrode line on the cell structure, wherein the first blocking layer is on at least one of an upper surface, a lower surface, and the upper and lower surfaces of the variable resistance layer, and the first blocking layer includes a metal layer or a carbon-containing conductive layer.