公开(公告)号：US10943812B2

公开(公告)日：2021-03-09

申请号：US16535808

申请日：2019-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Semyeong Jang ,  Bong-Soo Kim ,  Heejae Chae

IPC: H01L27/105 ,  H01L27/24 ,  H01L27/22 ,  H01L27/108 ,  H01L21/762

Abstract: A semiconductor device includes a first trench on the device region, a first device isolation layer in the first trench and defining an active pattern of the device region, a second trench on the interface region, and a second device isolation layer in the second trench. The second isolation layer includes a buried dielectric pattern, a dielectric liner pattern on the buried dielectric pattern, and a first gap-fill dielectric pattern on the dielectric liner pattern. The buried dielectric pattern includes a floor segment on a floor of the second trench, and a sidewall segment on a sidewall of the second trench. The sidewall segment has a thickness different from a thickness of the floor segment.

公开(公告)号：US20240290626A1

公开(公告)日：2024-08-29

申请号：US18587326

申请日：2024-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heejae Chae ,  Taejin Park ,  Hyunjin Lee ,  Hosang Lee ,  Yun Choi

IPC: H01L21/308 ,  H01L21/027 ,  H01L21/311 ,  H10B12/00

CPC classification number: H01L21/3086 ,  H01L21/0274 ,  H01L21/31144 ,  H10B12/50

Abstract: A method of manufacturing a semiconductor device includes forming an etch target layer in a surface of a cell region comprising a cell center region and a cell edge region surrounding the cell center region, forming an edge mask pattern on the surface of the cell edge region through a quadruple patterning process on the etch target layer, and forming a plurality of center mask patterns spaced apart from each other on the cell center region, and forming a first etch pattern on the cell edge region by etching the etch target layer by using the edge mask pattern and the plurality of center mask patterns as etch masks and forming a plurality of second etch patterns spaced apart from each other on the cell center region.

公开(公告)号：US20250071969A1

公开(公告)日：2025-02-27

申请号：US18623816

申请日：2024-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun Choi ,  Seungmuk Kim ,  Inwoo Kim ,  Sohyun Park ,  Hanseong Shin ,  Kiseok Lee ,  Hyunjin Lee ,  Hosang Lee ,  Hongjun Lee ,  Heejae Chae

IPC: H10B12/00 ,  H01L21/027 ,  H01L21/311

Abstract: A semiconductor device may include a plurality of active patterns disposed on a substrate, a gate structure extending in a first direction, a bit line structure extending in a second direction, and a plurality of capacitors electrically connected to the plurality of active patterns, respectively, the plurality of active patterns having a shape extending in a third direction oblique to the first and second directions, the gate structure passing through centers of the plurality of active patterns, the bit line structure connected to first end portions of the plurality of active patterns, the plurality of capacitors connected to second end portions of the plurality of active patterns, respectively, the first end portion and the second end portion positioned at opposite sides with respect to the gate structure, and the first end portion and the second end portion having point-symmetrical shapes with respect to a center of the active pattern.

公开(公告)号：US20240431097A1

公开(公告)日：2024-12-26

申请号：US18545328

申请日：2023-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjin Lee ,  Jongmin Kim ,  Kiseok Lee ,  Yun Choi ,  Inwoo Kim ,  Hui-Jung Kim ,  Sohyun Park ,  Heejae Chae

IPC: H10B12/00

Abstract: Disclosed is a semiconductor device comprising an active pattern including first and second edge parts spaced apart from each other in a first direction, a word line extending along a second direction between the first and second edge parts, a bit line extending along a third direction on the first edge part, a storage node contact on the second edge part, a first active pad between the bit line and the first edge part, and a second active pad between the storage node contact and the second edge part. The first active pad extends in the third direction more than the first edge part. The second active pad extends in a direction opposite to the third direction more than the second edge part.

公开(公告)号：US20230402518A1

公开(公告)日：2023-12-14

申请号：US18202085

申请日：2023-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Kyujin Kim ,  Bongsoo Kim ,  Huijung Kim ,  Pyung Moon ,  Chulkwon Park ,  Gyunghyun Yoon ,  Heejae Chae

IPC: H01L29/423 ,  H10B12/00 ,  H01L29/49

CPC classification number: H01L29/4236 ,  H10B12/315 ,  H01L29/4916

Abstract: An integrated circuit (IC) device includes a gate trench formed inside a substrate, the gate trench including a bottom portion and a sidewall portion, a gate electrode structure disposed apart from the bottom portion and the sidewall portion of the gate trench, the gate electrode structure including a gate electrode including a first sub-gate electrode formed in a lower portion of the gate trench and a second sub-gate electrode formed on the first sub-gate electrode and a gate capping layer formed on the second sub-gate electrode, and a gate insulating layer formed between the gate trench and the gate electrode structure, the gate insulating layer including a base insulating layer formed between the bottom portion and the sidewall portion of the gate trench and the gate electrode structure and a reinforcing insulating layer formed on a sidewall portion of the second sub-gate electrode.