公开(公告)号：US20250071969A1

公开(公告)日：2025-02-27

申请号：US18623816

申请日：2024-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun Choi ,  Seungmuk Kim ,  Inwoo Kim ,  Sohyun Park ,  Hanseong Shin ,  Kiseok Lee ,  Hyunjin Lee ,  Hosang Lee ,  Hongjun Lee ,  Heejae Chae

IPC: H10B12/00 ,  H01L21/027 ,  H01L21/311

Abstract: A semiconductor device may include a plurality of active patterns disposed on a substrate, a gate structure extending in a first direction, a bit line structure extending in a second direction, and a plurality of capacitors electrically connected to the plurality of active patterns, respectively, the plurality of active patterns having a shape extending in a third direction oblique to the first and second directions, the gate structure passing through centers of the plurality of active patterns, the bit line structure connected to first end portions of the plurality of active patterns, the plurality of capacitors connected to second end portions of the plurality of active patterns, respectively, the first end portion and the second end portion positioned at opposite sides with respect to the gate structure, and the first end portion and the second end portion having point-symmetrical shapes with respect to a center of the active pattern.

公开(公告)号：US12114475B2

公开(公告)日：2024-10-08

申请号：US17667195

申请日：2022-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Huijung Kim ,  Myeongdong Lee ,  Inwoo Kim ,  Sunghee Han

IPC: H01L23/528 ,  H10B12/00 ,  H01L23/522

CPC classification number: H10B12/0335 ,  H01L23/528 ,  H10B12/315 ,  H10B12/482 ,  H01L23/5226

Abstract: An integrated circuit device includes a substrate including active regions, a direct contact electrically connected to a first active region selected from the active regions, a buried contact plug electrically connected to a second active region selected from the active regions, the second active region adjacent to the first active region in a first horizontal direction, and including a conductive semiconductor layer, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction and electrically connected to the direct contact, a conductive landing pad extending toward the buried contact plug in a vertical direction, having a sidewall facing the bit line in the first horizontal direction, and including a metal, and an outer insulating spacer between the bit line and the conductive landing pad, in contact with the sidewall of the conductive landing pad, and spaced apart from the buried contact plug.

公开(公告)号：US20240431097A1

公开(公告)日：2024-12-26

申请号：US18545328

申请日：2023-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjin Lee ,  Jongmin Kim ,  Kiseok Lee ,  Yun Choi ,  Inwoo Kim ,  Hui-Jung Kim ,  Sohyun Park ,  Heejae Chae

IPC: H10B12/00

Abstract: Disclosed is a semiconductor device comprising an active pattern including first and second edge parts spaced apart from each other in a first direction, a word line extending along a second direction between the first and second edge parts, a bit line extending along a third direction on the first edge part, a storage node contact on the second edge part, a first active pad between the bit line and the first edge part, and a second active pad between the storage node contact and the second edge part. The first active pad extends in the third direction more than the first edge part. The second active pad extends in a direction opposite to the third direction more than the second edge part.

公开(公告)号：US20240414909A1

公开(公告)日：2024-12-12

申请号：US18442363

申请日：2024-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyun Park ,  Inwoo Kim ,  Jihun Lee ,  Seongtak Cho

IPC: H10B12/00 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes an active pattern on a substrate; a gate structure extending through an upper portion of the active pattern; a bit line structure on a central portion of the active pattern; a lower contact plug on each of opposite end portions of the active pattern; and an upper contact plug structure on the lower contact plug. The upper contact plug structure includes a first upper contact plug and a second upper contact plug on the first upper contact plug. The second upper contact plug contacts the first upper contact plug. The first upper contact plug includes a first metal pattern and a barrier pattern covering a lower surface and a sidewall of the first metal pattern. An upper surface of the bit line structure contacts a lower surface of the second upper contact plug and does not contact the barrier pattern.

公开(公告)号：US20240324182A1

公开(公告)日：2024-09-26

申请号：US18470537

申请日：2023-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongtak Cho ,  Inwoo Kim ,  Miso Myung ,  Jihun Lee

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/0335 ,  H10B12/315

Abstract: A semiconductor device includes a substrate that includes an active pattern, a bit line structure that crosses the active pattern, a storage node contact electrically connected to the active pattern next to the bit line structure, a spacer structure between a side surface of the bit line structure and the storage node contact, an upper surface of the spacer structure is at a vertical level lower than an upper surface of the bit line structure, an insulating pattern on the spacer structure, and a landing pad structure electrically connected to the storage node contact and on the spacer structure and the bit line structure. The landing pad structure include a first side surface in contact with the spacer structure, a second side surface in contact with the bit line structure, and a third side surface in contact with the insulating pattern.

公开(公告)号：US20250071967A1

公开(公告)日：2025-02-27

申请号：US18673537

申请日：2024-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyun Park ,  Inwoo Kim ,  Kiseok Lee

IPC: H10B12/00

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of contact plugs spaced apart from each other on the semiconductor substrate, a plurality of first landing pads spaced apart from each other on the plurality of contact plugs, a landing insulating layer surrounding upper sidewalls of the plurality of first landing pads and covering upper portions of the plurality of first landing pads, a stopper insulating layer disposed on the landing insulating layer, and a plurality of second landing pads spaced apart from each other on the plurality of first landing pads, passing through the stopper insulating layer, and buried in landing opening holes formed in the landing insulating layer, the plurality of second landing pads being electrically and respectively connected to the plurality of first landing pads.

公开(公告)号：US20220336465A1

公开(公告)日：2022-10-20

申请号：US17667195

申请日：2022-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Huijung Kim ,  Myeongdong Lee ,  Inwoo Kim ,  Sunghee Han

IPC: H01L27/108 ,  H01L23/528

Abstract: An integrated circuit device includes a substrate including active regions, a direct contact electrically connected to a first active region selected from the active regions, a buried contact plug electrically connected to a second active region selected from the active regions, the second active region adjacent to the first active region in a first horizontal direction, and including a conductive semiconductor layer, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction and electrically connected to the direct contact, a conductive landing pad extending toward the buried contact plug in a vertical direction, having a sidewall facing the bit line in the first horizontal direction, and including a metal, and an outer insulating spacer between the bit line and the conductive landing pad, in contact with the sidewall of the conductive landing pad, and spaced apart from the buried contact plug.