-
公开(公告)号：US11709537B2
公开(公告)日：2023-07-25
申请号：US17857526
申请日：2022-07-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ho-Yeon Jeon , Dae Hwan Kim , Young Hoon Lee
CPC classification number: G06F1/28 , G06F1/26 , G11C5/148 , G06F1/30 , G06F1/3203
Abstract: A semiconductor device and a power-off method of the semiconductor device, the semiconductor device including a first power source group including first and second power sources, a second power source group including a third power source and a power sequence controller. The power sequence controller performs power-on operations and power-off operations of the first to third power sources. The power sequence controller starts a power-off operation of the first power source group at a first time, and starts a power-off operation of the second power source group when the power voltage of the first power source group becomes a first voltage or when a first reference time has passed from the first time.
-
公开(公告)号：US12235698B2
公开(公告)日：2025-02-25
申请号：US18205014
申请日：2023-06-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ho-Yeon Jeon , Dae Hwan Kim , Young Hoon Lee
Abstract: A semiconductor device and a power-off method of the semiconductor device, the semiconductor device including a first power source group including first and second power sources, a second power source group including a third power source and a power sequence controller. The power sequence controller performs power-on operations and power-off operations of the first to third power sources. The power sequence controller starts a power-off operation of the first power source group at a first time, and starts a power-off operation of the second power source group when the power voltage of the first power source group becomes a first voltage or when a first reference time has passed from the first time.
-
公开(公告)号：US11379028B2
公开(公告)日：2022-07-05
申请号：US16933270
申请日：2020-07-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ho-Yeon Jeon , Dae Hwan Kim , Young Hoon Lee
Abstract: A semiconductor device and a power-off method of the semiconductor device, the semiconductor device including a first power source group including first and second power sources, a second power source group including a third power source and a power sequence controller. The power sequence controller performs power-on operations and power-off operations of the first to third power sources. The power sequence controller starts a power-off operation of the first power source group at a first time, and starts a power-off operation of the second power source group when the power voltage of the first power source group becomes a first voltage or when a first reference time has passed from the first time.
-
Patent Agency Ranking
公开(公告)号：US10372156B2
公开(公告)日：2019-08-06
申请号：US15388366
申请日：2016-12-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youn-Sik Choi , Jin-Ook Song , Ho-Yeon Jeon , Jae-Gon Lee
Abstract: A system-on-chip (SoC) comprises a clock management unit (CMU) including a first clock generator and a second clock generator, the first and second clock generators being configured to generate clock signals. The SoC comprises at least one logic block configured to request the clock signals from the CMU according to a full handshake method and receive the clock signals from the CMU in response to the request. The first clock generator and the second clock generator are configured to communicate according to the full handshake method.
-
公开(公告)号：US10901452B2
公开(公告)日：2021-01-26
申请号：US16512849
申请日：2019-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youn-Sik Choi , Jin-Ook Song , Ho-Yeon Jeon , Jae-Gon Lee
Abstract: A system-on-chip (SoC) comprises a clock management unit (CMU) including a first clock generator and a second clock generator, the first and second clock generators being configured to generate clock signals. The SoC comprises at least one logic block configured to request the clock signals from the CMU according to a full handshake method and receive the clock signals from the CMU in response to the request. The first clock generator and the second clock generator are configured to communicate according to the full handshake method.
-
公开(公告)号：US10725516B2
公开(公告)日：2020-07-28
申请号：US15922968
申请日：2018-03-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ho-Yeon Jeon , Dae Hwan Kim , Young Hoon Lee
IPC: G06F1/32 , G06F1/28 , G06F1/26 , G11C5/14 , G06F1/3203
Abstract: A semiconductor device and a power-off method of the semiconductor device, the semiconductor device including a first power source group including first and second power sources, a second power source group including a third power source and a power sequence controller. The power sequence controller performs power-on operations and power-off operations of the first to third power sources. The power sequence controller starts a power-off operation of the first power source group at a first time, and starts a power-off operation of the second power source group when the power voltage of the first power source group becomes a first voltage or when a first reference time has passed from the first time.
-
公开(公告)号：US10475501B2
公开(公告)日：2019-11-12
申请号：US15946992
申请日：2018-04-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ho-Yeon Jeon , Ah Chan Kim , Min Joung Lee , Youn-Sik Choi
Abstract: A semiconductor device includes a first serializer configured to collect at least one event in a first domain to generate a first serial data stream and transmit the first serial data stream periodically at a first period, a first de-serializer configured to receive the first serial data stream to restore the first serial data stream into first parallel data streams, the first parallel data stream encoding first parallel data items, a timer configured to provide a clock signal having a second period, a direct memory access (DMA) configured to capture the first parallel data items periodically at a second period using the clock signal to generate capture data items, and a first memory configured to store the capture data items. The addresses of the first memory at which the respective capture data items are stored are arranged in an order that the respective capture data items are captured.
-
公开(公告)号：US09703366B2
公开(公告)日：2017-07-11
申请号：US14740918
申请日：2015-06-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ho-Yeon Jeon
CPC classification number: G06F1/3296 , G06F1/324 , G06F1/325 , G06F1/3275 , G11C5/14 , Y02D10/126 , Y02D10/14 , Y02D10/172
Abstract: A system on chip (SoC) includes a plurality of function circuits including a plurality of logic circuits and a plurality of function circuits each of which includes a logic circuit and a memory, and a plurality of power path controllers respectively coupled to a plurality of first power sources at first input terminals, commonly coupled to a second power source at second input terminals, and respectively coupled to the memories at output terminals. The logic circuits are respectively coupled to the first power sources, and configured to be supplied with a plurality of first power supply voltages from the first power sources, respectively. Each of the memories is configured to be selectively supplied, by a corresponding one of the power path controllers, with one of a corresponding one of the first power supply voltages from a corresponding one of the first power sources and a second power supply voltage from the second power source.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.022 seconds)
