公开(公告)号：US20250036521A1

公开(公告)日：2025-01-30

申请号：US18770435

申请日：2024-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungkyu Lee ,  Seongmuk Kang ,  Jae-Gon Lee ,  Kyomin Sohn ,  Yeonggeol Song ,  Kijun Lee

IPC: G06F11/10

Abstract: An example CXL (Compute eXpress Link)-based memory module includes a memory device and a controller. The memory device includes a plurality of volatile memory cells and stores data or reads the stored data. The controller communicates with a host device through a CXL interface and controls the memory device. The controller includes an error correction code (ECC) circuit that generates a first codeword by adding a parity vector generated based on Reed-Solomon encoding to data received from the host device, an error injecting circuit that generates an error symbol and generates a second codeword by injecting the error symbol into at least a portion of the first codeword, and a memory device interface that controls the memory device such that the second codeword where the error symbol is injected is stored in the memory device. The controller determines a number of error symbols to be injected into the second codeword.

公开(公告)号：US10901452B2

公开(公告)日：2021-01-26

申请号：US16512849

申请日：2019-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn-Sik Choi ,  Jin-Ook Song ,  Ho-Yeon Jeon ,  Jae-Gon Lee

IPC: G06F1/06 ,  H04J3/06 ,  H04L7/00 ,  G06F1/04

Abstract: A system-on-chip (SoC) comprises a clock management unit (CMU) including a first clock generator and a second clock generator, the first and second clock generators being configured to generate clock signals. The SoC comprises at least one logic block configured to request the clock signals from the CMU according to a full handshake method and receive the clock signals from the CMU in response to the request. The first clock generator and the second clock generator are configured to communicate according to the full handshake method.

公开(公告)号：US11296416B2

公开(公告)日：2022-04-05

申请号：US16608621

申请日：2018-04-19

Applicant: Samsung Electronics Co., Ltd. ,  Hongik University Industry-Academia Cooperation Foundation

Inventor： Jae-Seok Park ,  Jeong-Hae Lee ,  Jae-Hyun Park ,  Kwi-Seob Um ,  Young-Ho Ryu ,  Chang-Hyun Lee ,  Sang-Wook Kwon ,  Sung-Bum Park ,  Jae-Gon Lee ,  Sang-Wook Chi

IPC: H01Q9/04 ,  H01Q1/48 ,  H01Q15/14 ,  H01Q1/24 ,  H01Q3/36

Abstract: In various embodiments, a metamaterial structure antenna may comprise: a feed line for feeding a signal; a ground plane comprising a cross-shaped aperture forming circular polarization on the basis of a magnetic field induced by the fed signal; and a patch plane formed parallel to the ground plane which emits electromagnetic waves on the basis of the circular polarization.

公开(公告)号：US12164802B2

公开(公告)日：2024-12-10

申请号：US18142331

申请日：2023-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chon Yong Lee ,  Jae-Gon Lee ,  Kyung-Chang Ryoo ,  Kyunghan Lee ,  Hyeyoung Ryu

IPC: G06F3/06

Abstract: A method of operating storage devices, a memory device, a host device, and a switch, is provided. The method includes: receiving, by the memory device, a first request corresponding to target user data from the host device; generating, by the memory device, first input/output (I/O) stream information based on telemetry information corresponding to the storage devices and map data in a buffer memory of the memory device based on the first request, wherein the first I/O stream information indicates a data path between a first storage device of the storage devices and the host device; providing, by the memory device, a first redirection request including the first request and the first I/O stream information to the host device or the first storage device through the switch; and processing the target user data according to the first I/O stream information in the first redirection request.

公开(公告)号：US20230359394A1

公开(公告)日：2023-11-09

申请号：US18134359

申请日：2023-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Gon Lee ,  Kyunghan Lee ,  Chon Yong Lee

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0631 ,  G06F3/0625 ,  G06F3/0679

Abstract: An operating method of a memory device which communicates with a first storage device and a second storage device through an interface circuit is provided. The method includes receiving, from a host device, a first request including a command and a first logical block address; obtaining, based on the first logical block address, a first physical block address with reference to first map data dedicated for the first storage device; and sending, to the first storage device through the interface circuit, a second request including the first physical block address and the command.

公开(公告)号：US20230342073A1

公开(公告)日：2023-10-26

申请号：US18344837

申请日：2023-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chon Yong Lee ,  Jae-Gon Lee ,  Kyunghan Lee

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory expander includes a memory device that stores a plurality of task data. A controller controls the memory device. The controller receives metadata and a management request from an external central processing unit (CPU) through a compute express link (CXL) interface and operates in a management mode in response to the management request. In the management mode, the controller receives a read request and a first address from an accelerator through the CXL interface and transmits one of the plurality of task data to the accelerator based on the metadata in response to the read request.

公开(公告)号：US11275708B2

公开(公告)日：2022-03-15

申请号：US16952681

申请日：2020-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-yeon Jeon ,  Jae-Gon Lee ,  Youn-Sik Choi ,  Min-joung Lee ,  Jin-ook Song

IPC: G06F13/42 ,  G06F13/364

Abstract: In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.

公开(公告)号：US11048645B2

公开(公告)日：2021-06-29

申请号：US16103058

申请日：2018-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Young Lim ,  Dimin Niu ,  Jae-Gon Lee

IPC: G06F3/06 ,  G06F12/14 ,  G06F21/79 ,  G06F16/11 ,  G06F16/174 ,  G11C16/26 ,  G11C29/52 ,  G11C16/04 ,  G11C16/10 ,  G06F11/10

Abstract: A memory module includes a random access memory (RAM) device that includes a first storage region and a second storage region, a nonvolatile memory device, and a controller that controls the RAM device or the nonvolatile memory device under control of a host. The controller includes a data buffer that temporarily stores first data received from the host, and a buffer returning unit that transmits first release information to the host when the first data are moved from the data buffer to the first storage region or the second storage region of the RAM device and transmits second release information to the host when the first data are moved from the second storage region to the nonvolatile memory device.

公开(公告)号：US11726701B2

公开(公告)日：2023-08-15

申请号：US17509669

申请日：2021-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chon Yong Lee ,  Jae-Gon Lee ,  Kyunghan Lee

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/28 ,  G06F9/451 ,  G06F12/02 ,  G06F13/38

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory expander includes a memory device that stores a plurality of task data. A controller controls the memory device. The controller receives metadata and a management request from an external central processing unit (CPU) through a compute express link (CXL) interface and operates in a management mode in response to the management request. In the management mode, the controller receives a read request and a first address from an accelerator through the CXL interface and transmits one of the plurality of task data to the accelerator based on the metadata in response to the read request.

公开(公告)号：US10372156B2

公开(公告)日：2019-08-06

申请号：US15388366

申请日：2016-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn-Sik Choi ,  Jin-Ook Song ,  Ho-Yeon Jeon ,  Jae-Gon Lee

IPC: G06F1/04 ,  G06F1/06 ,  H04J3/06 ,  H04L7/00

Abstract: A system-on-chip (SoC) comprises a clock management unit (CMU) including a first clock generator and a second clock generator, the first and second clock generators being configured to generate clock signals. The SoC comprises at least one logic block configured to request the clock signals from the CMU according to a full handshake method and receive the clock signals from the CMU in response to the request. The first clock generator and the second clock generator are configured to communicate according to the full handshake method.