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公开(公告)号:US11888063B2
公开(公告)日:2024-01-30
申请号:US17862961
申请日:2022-07-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Weonhong Kim , Wandon Kim , Hyeonjun Baek , Sangjin Hyun
IPC: H01L29/78 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/786 , H01L21/28
CPC classification number: H01L29/78391 , H01L21/28088 , H01L29/0673 , H01L29/40111 , H01L29/42392 , H01L29/4908 , H01L29/4966 , H01L29/516 , H01L29/6684 , H01L29/7851 , H01L29/78696
Abstract: A semiconductor device includes a substrate including an active pattern, a gate electrode crossing the active pattern in a plan view, and a ferroelectric pattern interposed between the active pattern and the gate electrode. The gate electrode includes a work function metal pattern disposed on the ferroelectric pattern, and an electrode pattern filling a recess formed in an upper portion of the work function metal pattern. A top surface of a topmost portion of the ferroelectric pattern is lower than a bottom surface of the recess.
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公开(公告)号:US11411106B2
公开(公告)日:2022-08-09
申请号:US17176248
申请日:2021-02-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Weonhong Kim , Wandon Kim , Hyeonjun Baek , Sangjin Hyun
IPC: H01L29/78 , H01L29/51 , H01L29/49 , H01L21/28 , H01L29/66 , H01L29/423 , H01L29/786 , H01L29/06
Abstract: A semiconductor device includes a substrate including an active pattern, a gate electrode crossing the active pattern in a plan view, and a ferroelectric pattern interposed between the active pattern and the gate electrode. The gate electrode includes a work function metal pattern disposed on the ferroelectric pattern, and an electrode pattern filling a recess formed in an upper portion of the work function metal pattern. A top surface of a topmost portion of the ferroelectric pattern is lower than a bottom surface of the recess.
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公开(公告)号:US10985275B2
公开(公告)日:2021-04-20
申请号:US16503790
申请日:2019-07-05
Applicant: Samsung Electronics Co., Ltd.
Inventor: Weonhong Kim , Wandon Kim , Hyeonjun Baek , Sangjin Hyun
IPC: H01L29/78 , H01L21/28 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/786
Abstract: A semiconductor device includes a substrate including an active pattern, a gate electrode crossing the active pattern in a plan view, and a ferroelectric pattern interposed between the active pattern and the gate electrode. The gate electrode includes a work function metal pattern disposed on the ferroelectric pattern, and an electrode pattern filling a recess formed in an upper portion of the work function metal pattern. A top surface of a topmost portion of the ferroelectric pattern is lower than a bottom surface of the recess.
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公开(公告)号:US10950709B2
公开(公告)日:2021-03-16
申请号:US16458412
申请日:2019-07-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jeonghyuk Yim , Wandon Kim , Weonhong Kim , Jongho Park , Hyeonjun Baek , Byounghoon Lee , Sangjin Hyun
IPC: H01L29/78 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/786 , H01L29/51 , H01L21/28 , H01L29/66 , H01L21/8238 , H01L29/08
Abstract: A semiconductor device includes a substrate including first and second active regions, first and second active patterns disposed on the first and second active regions, respectively, first and second gate electrodes crossing the first and second active patterns, respectively, a first gate insulating pattern interposed between the first active pattern and the first gate electrode, and a second gate insulating pattern interposed between the second active pattern and the second gate electrode. The first gate insulating pattern includes a first dielectric pattern and a first ferroelectric pattern disposed on the first dielectric pattern. The second gate insulating pattern includes a second dielectric pattern. A threshold voltage of a transistor in the first active region is different from a threshold voltage of a transistor in the second active region.
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