公开(公告)号：US11888063B2

公开(公告)日：2024-01-30

申请号：US17862961

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Weonhong Kim ,  Wandon Kim ,  Hyeonjun Baek ,  Sangjin Hyun

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786 ,  H01L21/28

CPC classification number: H01L29/78391 ,  H01L21/28088 ,  H01L29/0673 ,  H01L29/40111 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate including an active pattern, a gate electrode crossing the active pattern in a plan view, and a ferroelectric pattern interposed between the active pattern and the gate electrode. The gate electrode includes a work function metal pattern disposed on the ferroelectric pattern, and an electrode pattern filling a recess formed in an upper portion of the work function metal pattern. A top surface of a topmost portion of the ferroelectric pattern is lower than a bottom surface of the recess.

公开(公告)号：US11342328B2

公开(公告)日：2022-05-24

申请号：US16943208

申请日：2020-07-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guyoung Cho ,  Subin Shin ,  Donghyun Roh ,  Byung-Suk Jung ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78

Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.

公开(公告)号：US20220077295A1

公开(公告)日：2022-03-10

申请号：US17524259

申请日：2021-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonkeun CHUNG ,  Heonbok Lee ,  Chunghwan Shin ,  Youngsuk Chai ,  Sangjin Hyun

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device includes a substrate having an active pattern therein, a gate electrode extending across the active pattern and a source/drain region on the active pattern laterally adjacent the gate electrode. The device further includes a contact structure including a first contact on the source/drain region, a second contact on the first contact and a spacer on sidewalls of the first and second contacts.

公开(公告)号：US10892342B2

公开(公告)日：2021-01-12

申请号：US16803130

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun Chung ,  Jae-Jung Kim ,  Jinkyu Jang ,  Sangyong Kim ,  Hoonjoo Na ,  Dongsoo Lee ,  Sangjin Hyun

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/06 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L27/11 ,  H01L21/28 ,  B82Y10/00

Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.

公开(公告)号：US10475898B2

公开(公告)日：2019-11-12

申请号：US15938716

申请日：2018-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun Chung ,  Jae-Jung Kim ,  Jinkyu Jang ,  Sangyong Kim ,  Hoonjoo Na ,  Dongsoo Lee ,  Sangjin Hyun

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/51 ,  H01L27/11 ,  H01L29/06

Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.

公开(公告)号：US20180331103A1

公开(公告)日：2018-11-15

申请号：US16017024

申请日：2018-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun Chung ,  Gigwan Park ,  Huyong Lee ,  TaekSoo Jeon ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L21/28114 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/435 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of the gate electrode. The gate electrode includes a first metal pattern adjacent to the active pattern. The first metal pattern has a first portion parallel to the sidewall and a second portion parallel to the substrate. A top surface of the first portion has a descent in a direction from the spacer towards the second portion.

公开(公告)号：US09991357B2

公开(公告)日：2018-06-05

申请号：US15186982

申请日：2016-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol Song ,  Wandon Kim ,  Hoonjoo Na ,  Suyoung Bae ,  Hyeok-Jun Son ,  Sangjin Hyun

IPC: H01L27/088 ,  H01L29/51 ,  H01L27/085 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/085 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518

Abstract: A semiconductor device includes a semiconductor substrate including multiple active regions having a common conductivity type and separate, respective gate electrodes on the separate active regions. Different high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. Different quantities of high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. The different high-k dielectric layers may include different work-function adjusting materials.

公开(公告)号：US20170186746A1

公开(公告)日：2017-06-29

申请号：US15372876

申请日：2016-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun Chung ,  Gigwan Park ,  Huyong Lee ,  TaekSoo Jeon ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L27/0922 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/435 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of the gate electrode. The gate electrode includes a first metal pattern adjacent to the active pattern. The first metal pattern has a first portion parallel to the sidewall and a second portion parallel to the substrate. A top surface of the first portion has a descent in a direction from the spacer towards the second portion.

公开(公告)号：US20130316525A1

公开(公告)日：2013-11-28

申请号：US13770709

申请日：2013-02-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HyeokJun Son ,  Sangjin Hyun ,  Sangbom Kang ,  SungKee Han ,  Sughun Hong ,  Hyung-seok Hong

IPC: H01L21/8238

CPC classification number: H01L21/823857

Abstract: A semiconductor device including a selectively nitrided gate insulating layer may be fabricated by a method that includes forming a first gate insulating layer on a substrate having a first region and a second region, performing a nitridation process on the first gate insulating layer, removing the first gate insulating layer from at least a portion of the first region to expose at least a portion of the substrate, forming a second gate insulating layer on at least the exposed portion of the first region of the substrate, thermally treating the first and second gate insulating layers in an oxygen atmosphere, forming a high-k dielectric on the first and second gate insulating layers, and forming a metal gate electrode on the high-k dielectric.

Abstract translation: 可以通过包括在具有第一区域和第二区域的衬底上形成第一栅极绝缘层的方法来制造包括选择性氮化栅极绝缘层的半导体器件，在第一栅极绝缘层上进行氮化处理，去除第一栅极绝缘层 栅极绝缘层，以从第一区域的至少一部分露出至少一部分基板，在至少基板的第一区域的暴露部分上形成第二栅极绝缘层，热处理第一和第二栅极绝缘层 层，在第一和第二栅极绝缘层上形成高k电介质，并在高k电介质上形成金属栅电极。

公开(公告)号：US12021080B2

公开(公告)日：2024-06-25

申请号：US18353214

申请日：2023-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo Lee ,  Wonkeun Chung ,  Hoonjoo Na ,  Suyoung Bae ,  Jaeyeol Song ,  Jonghan Lee ,  HyungSuk Jung ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/823842 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78696

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.