公开(公告)号：US12119331B2

公开(公告)日：2024-10-15

申请号：US17677453

申请日：2022-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Gyuho Kang ,  Heewon Kim ,  Sechul Park ,  Jongho Park ,  Junyoung Park

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/32 ,  H01L23/49833 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/08237 ,  H01L2224/32225 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.

公开(公告)号：US11948994B2

公开(公告)日：2024-04-02

申请号：US17531903

申请日：2021-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghoon Lee ,  Jongho Park ,  Wandon Kim ,  Sangjin Hyun

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/3215

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L21/3115 ,  H01L21/3215

Abstract: A semiconductor device includes a substrate having first and second active regions, first and second active patterns on the first and second active regions, first and second gate electrodes running across the first and second active patterns, and a high-k dielectric layer between the first active pattern and the first gate electrode and between the second active pattern and the second gate electrode. The first gate electrode includes a work function metal pattern and an electrode pattern. The second gate electrode includes a first work function metal pattern, a second work function metal pattern, and an electrode pattern. The first work function metal pattern contains the same impurity as that of the high-k dielectric layer. An impurity concentration of the first work function metal pattern of the second gate electrode is greater than that of the work function metal pattern of the first gate electrode.

公开(公告)号：US20230343560A1

公开(公告)日：2023-10-26

申请号：US18217043

申请日：2023-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Jaeho Kwak ,  Boeun Jang ,  Seokyeon Hwang ,  Yongseok Seo ,  Sangsoo Kim ,  Seunghwan Kim ,  Jongho Park ,  Yongkwan Lee ,  Jongho Lee ,  Daewook Kim ,  Wonpil Lee ,  Changkyu Choi

IPC: H01J37/32 ,  C23C16/455

CPC classification number: H01J37/32449 ,  C23C16/45504 ,  C23C16/45589 ,  H01J37/32633 ,  H01J37/32357 ,  C23C16/45591 ,  C23C16/45502 ,  C23C16/4583

Abstract: A surface treatment apparatus and a surface treatment system having the same are disclosed. The surface treatment apparatus includes a process chamber in which the surface treatment process is conducted, a plasma generator for generating process radicals as a plasma state for the surface treatment process, the plasma generator being positioned outside of the process chamber and connected to the process chamber by a supply duct, a heat exchanger arranged on the supply duct and cooling down temperature of the process radicals passing through the supply duct and a flow controller controlling the process radicals to flow out of the process chamber. The flow controller is connected to a discharge duct through which the process radicals are discharged outside the process chamber. The plasma surface treatment process is conducted to the package structure having minute mounting gap without the damages to the IC chip and the board.

公开(公告)号：US11387236B2

公开(公告)日：2022-07-12

申请号：US16840880

申请日：2020-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho Park ,  Jaeyeol Song ,  Wandon Kim ,  Byounghoon Lee ,  Musarrat Hasan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes first and second active patterns on first and second active regions of a substrate, respectively, a pair of first source/drain patterns and a first channel pattern therebetween which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern therebetween which are in an upper portion of the second active pattern, and first and second gate electrodes intersecting the first and second channel patterns, respectively. Each of the first and second gate electrodes includes a first metal pattern adjacent to a corresponding one of the first and second channel patterns. The first and second channel patterns include SiGe. A Ge concentration of the second channel pattern is higher than a Ge concentration of the first channel pattern. A thickness of the first metal pattern of the second gate electrode is greater than a thickness of the first metal pattern of the first gate electrode.

公开(公告)号：US11224101B2

公开(公告)日：2022-01-11

申请号：US16364705

申请日：2019-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilyoung Lee ,  Jinseok Kwon ,  Jongho Park ,  Jinhee Cho ,  Kumchul Hwang

IPC: H05B6/06 ,  H05B3/68 ,  H05B1/02

Abstract: A cooking apparatus is provided. The cooking apparatus includes heating coils, an input apparatus receiving input of output levels for each of the heating coils, inverters providing driving power to each of the heating coils separately, and a processor controlling the inverters based on the inputted output levels. The processor is configured to predict the power consumption of each of the heating coils based on the inputted output levels, and based on the sum of the predicted power consumption being greater than a predetermined power value, determine a subject heating coil based on the predicted power consumption for each heating coil and history information on power adjustment of the heating coils, and control an inverter corresponding to the subject heating coil such that the subject heating coil operates at a smaller output level than a current output level.

公开(公告)号：US11147001B2

公开(公告)日：2021-10-12

申请号：US16630672

申请日：2018-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihyeon Choi ,  Jongho Park ,  Sangyeon Won ,  Hanseok Kim ,  Daewoo Lee

IPC: H04W36/00 ,  H04W84/12

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). According to various embodiments of the present disclosure, a device of a terminal in a wireless communication system can include at least one transceiver and at least one processor operationally coupled with at least one transceiver. At least one processor can receive configuration information from a first network node for a first radio access technology (RAT), measure a first quality for a first signal of the first RAT and a second quality for a second signal of a second RAT on the basis of the received configuration information, and determine, whether a handover to a second network for the second RAT is performed, on the basis of the measured first quality or the measured second quality. The configuration information can include parameters for the handover between the first RAT and the second RAT.

公开(公告)号：US20210242190A1

公开(公告)日：2021-08-05

申请号：US17168706

申请日：2021-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Kyonghwan Koh ,  Sangsoo Kim ,  Seunghwan Kim ,  Jongho Park ,  Yongkwan Lee

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A method of manufacturing a semiconductor package includes forming a laser reactive polymer layer on a substrate; mounting a semiconductor device on the substrate; irradiating at least a portion of the laser reactive polymer layer below the semiconductor device with a laser having a wavelength capable of penetrating through the semiconductor device on the substrate to modify the laser reactive polymer layer to have a hydrophilic functional group; and forming a first encapsulation material layer between the semiconductor device and the substrate.

公开(公告)号：US10950709B2

公开(公告)日：2021-03-16

申请号：US16458412

申请日：2019-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyuk Yim ,  Wandon Kim ,  Weonhong Kim ,  Jongho Park ,  Hyeonjun Baek ,  Byounghoon Lee ,  Sangjin Hyun

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08

Abstract: A semiconductor device includes a substrate including first and second active regions, first and second active patterns disposed on the first and second active regions, respectively, first and second gate electrodes crossing the first and second active patterns, respectively, a first gate insulating pattern interposed between the first active pattern and the first gate electrode, and a second gate insulating pattern interposed between the second active pattern and the second gate electrode. The first gate insulating pattern includes a first dielectric pattern and a first ferroelectric pattern disposed on the first dielectric pattern. The second gate insulating pattern includes a second dielectric pattern. A threshold voltage of a transistor in the first active region is different from a threshold voltage of a transistor in the second active region.

公开(公告)号：US10784260B2

公开(公告)日：2020-09-22

申请号：US16116295

申请日：2018-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho Park ,  Wandon Kim ,  Jeonghyuk Yim ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L29/49 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor device includes first, second, and third transistors on a substrate and having different threshold voltages from each other, each of the first, second, and third transistors including: a gate insulating layer, a first work function metal layer, and a second work function metal layer. The first work function metal layer of the first transistor may include a first sub-work function layer, the first work function metal layer of the second transistor may include a second sub-work function layer, the first work function metal layer of the third transistor may include a third sub-work function layer, and the first, second, and third sub-work function layers may have different work functions from each other.

公开(公告)号：US12080712B2

公开(公告)日：2024-09-03

申请号：US17712272

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon Lee ,  Jongho Park ,  Wandon Kim ,  Sangjin Hyun

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/4966 ,  H01L21/02532 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device includes a plurality of semiconductor patterns that are sequentially stacked and spaced apart from each other on a substrate, and a gate electrode on the plurality of semiconductor patterns. The gate electrode includes a capping pattern and a work function pattern that are sequentially stacked on the plurality of semiconductor patterns. The capping pattern includes a first metal nitride layer including a first metal element, and a second metal nitride layer including a second metal element whose work function is greater than a work function of the first metal element. The first metal nitride layer is disposed between the second metal nitride layer and the plurality of semiconductor patterns. The first metal nitride layer is thinner than the second metal nitride layer.