公开(公告)号：US20220130437A1

公开(公告)日：2022-04-28

申请号：US17239647

申请日：2021-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEHWAN PARK ,  JINYOUNG KIM ,  YOUNGDEOK SEO ,  ILHAN PARK

IPC: G11C7/10 ,  G11C7/14 ,  G11C7/18 ,  G11C8/08

Abstract: A storage device includes at least one non-volatile memory device and a controller configured to control the at least one non-volatile memory device. The at least one non-volatile memory device performs an on-chip valley search (OVS) operation by latching a read command at an edge of a write enable (WE) signal according to a command latch enable (CLE) signal and an address latch enable (ALE) signal. The controller receives detection information according to the OVS operation from the at least one non-volatile memory device in response to a specific command. The OVS operation includes a first OVS operation using a read level and a second OVS operation using a changed read level.

公开(公告)号：US20240319874A1

公开(公告)日：2024-09-26

申请号：US18610556

申请日：2024-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUYONG KIM ,  ILHAN PARK

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0656 ,  G06F3/0679

Abstract: A memory device includes a first memory cell array and a second memory cell array, a first page buffer and a second page buffer configured to read data from the first memory cell array and the second memory cell array, respectively; and a first compression circuit configured to compress first soft decision data into first compressed data by encoding a location of a bit having a first value among bits of the first soft decision data, the first soft decision data being obtained from the first memory cell array by using a plurality of soft read voltages, wherein the first compression circuit is further configured to compress the first soft decision data into the first compressed data while second hard decision data is being output, the second hard decision data being read from the second memory cell array by using a hard read voltage.

公开(公告)号：US20220189575A1

公开(公告)日：2022-06-16

申请号：US17376932

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGDEOK SEO ,  WOOHYUN KANG ,  JINYOUNG KIM ,  KANGHO ROH ,  SEHWAN PARK ,  ILHAN PARK ,  HEETAI OH ,  HEEWON LEE ,  SILWAN CHANG ,  SANGHYUN CHOI

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C7/10 ,  G06N20/00

Abstract: A memory device may determine cell count information from a threshold voltage distribution of memory cells and may determine a detection case based on cell count information when correction of an error in read data, received from the memory device performing a read operation, fails. The memory controller may control the memory device to perform a read operation using a development time determined in consideration of an offset voltage of a read voltage corresponding to the detection case. When correction of the error in the read data fails again, the memory controller may control the memory device to perform a read operation using a corrected read voltage generated using a dynamic offset voltage obtained by inputting the cell count information to a machine learning model.

公开(公告)号：US20220139483A1

公开(公告)日：2022-05-05

申请号：US17336378

申请日：2021-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUNHYANG PARK ,  JINYOUNG KIM ,  JISANG LEE ,  SEHWAN PARK ,  ILHAN PARK

IPC: G11C29/42 ,  G11C29/44 ,  G11C16/26 ,  G11C16/04 ,  G11C16/34

Abstract: A reading method for a non-volatile memory device, includes performing a normal read operation using a default read level in response to a first read command; and performing a read operation using a multiple on-chip valley search (OVS) sensing operation in response to a second read command, when read data read in the normal read operation are uncorrectable.

公开(公告)号：US20220115073A1

公开(公告)日：2022-04-14

申请号：US17341837

申请日：2021-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNGMIN PARK ,  KYUNGHOON SUNG ,  ILHAN PARK ,  JISANG LEE ,  JOON SUC JANG ,  SANGHYUN JOO

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/10 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A nonvolatile memory device includes cell strings commonly connected between bitlines and a source line where the cell strings are grouped into memory blocks. During a precharge period, channels of the cell strings of a selected memory block are precharged by applying a gate induced drain leakage (GIDL) on voltage to gates of GIDL transistors included in the cell strings of the selected memory block where the GIDL on voltage has a voltage level to induce GIDL. During the precharge period, precharge of channels of the cell strings of an unselected memory block are prevented by controlling a gate voltage of GIDL transistors included in the cell strings of the unselected memory block to prevent the GIDL. During a program execution period after the precharge period, memory cells of the selected memory block connected to a selected wordline are programmed by applying a program voltage to the selected wordline.