公开(公告)号：US20160233104A1

公开(公告)日：2016-08-11

申请号：US14976296

申请日：2015-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： NAM-GUN KIM ,  JINYOUNG KIM ,  JONGCHEON KIM ,  CHANMl LEE ,  SUNGGIL CHOI ,  HYUN-CHUL YOON

IPC: H01L21/308 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/3213

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/11531

Abstract: A method of forming a semiconductor pattern can include providing an etching target layer. A hard mask pattern can be formed on the etching target layer using photolithography. First spacers can be formed on opposing sidewalls of the hard mask pattern and the hard mask pattern can be removed from between the first spacers to provide a first double patterning pattern self-aligned to the hard mask pattern. The planarization of top surfaces of the first double patterning pattern can be increased to provide a smoothed first double patterning pattern.

Abstract translation: 形成半导体图案的方法可以包括提供蚀刻目标层。 可以使用光刻法在蚀刻目标层上形成硬掩模图案。 可以在硬掩模图案的相对侧壁上形成第一间隔物，并且可以在第一间隔物之间​​移除硬掩模图案，以提供与硬掩模图案自对准的第一双重图案图案图案。 可以增加第一双图形图案的顶表面的平面化，以提供平滑的第一双图案图案。

公开(公告)号：US20220130437A1

公开(公告)日：2022-04-28

申请号：US17239647

申请日：2021-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEHWAN PARK ,  JINYOUNG KIM ,  YOUNGDEOK SEO ,  ILHAN PARK

IPC: G11C7/10 ,  G11C7/14 ,  G11C7/18 ,  G11C8/08

Abstract: A storage device includes at least one non-volatile memory device and a controller configured to control the at least one non-volatile memory device. The at least one non-volatile memory device performs an on-chip valley search (OVS) operation by latching a read command at an edge of a write enable (WE) signal according to a command latch enable (CLE) signal and an address latch enable (ALE) signal. The controller receives detection information according to the OVS operation from the at least one non-volatile memory device in response to a specific command. The OVS operation includes a first OVS operation using a read level and a second OVS operation using a changed read level.

公开(公告)号：US20200027877A1

公开(公告)日：2020-01-23

申请号：US16437169

申请日：2019-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINYOUNG KIM ,  YURI MASUOKA

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/36 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor device includes: a substrate including a first well region; a gate electrode disposed on the substrate; a semiconductor pattern disposed between the substrate and the gate electrode; a plurality of source/drain patterns disposed on the substrate and on opposing sides of the gate electrode; an impurity layer disposed in the substrate and between the semiconductor pattern and the first well region; and a barrier layer disposed in the substrate and between the semiconductor pattern and the impurity layer. The barrier layer includes oxygen.

公开(公告)号：US20220189575A1

公开(公告)日：2022-06-16

申请号：US17376932

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGDEOK SEO ,  WOOHYUN KANG ,  JINYOUNG KIM ,  KANGHO ROH ,  SEHWAN PARK ,  ILHAN PARK ,  HEETAI OH ,  HEEWON LEE ,  SILWAN CHANG ,  SANGHYUN CHOI

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C7/10 ,  G06N20/00

Abstract: A memory device may determine cell count information from a threshold voltage distribution of memory cells and may determine a detection case based on cell count information when correction of an error in read data, received from the memory device performing a read operation, fails. The memory controller may control the memory device to perform a read operation using a development time determined in consideration of an offset voltage of a read voltage corresponding to the detection case. When correction of the error in the read data fails again, the memory controller may control the memory device to perform a read operation using a corrected read voltage generated using a dynamic offset voltage obtained by inputting the cell count information to a machine learning model.

公开(公告)号：US20220139483A1

公开(公告)日：2022-05-05

申请号：US17336378

申请日：2021-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUNHYANG PARK ,  JINYOUNG KIM ,  JISANG LEE ,  SEHWAN PARK ,  ILHAN PARK

IPC: G11C29/42 ,  G11C29/44 ,  G11C16/26 ,  G11C16/04 ,  G11C16/34

Abstract: A reading method for a non-volatile memory device, includes performing a normal read operation using a default read level in response to a first read command; and performing a read operation using a multiple on-chip valley search (OVS) sensing operation in response to a second read command, when read data read in the normal read operation are uncorrectable.

公开(公告)号：US20210193706A1

公开(公告)日：2021-06-24

申请号：US16934278

申请日：2020-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINYOUNG KIM ,  EUIYEOL KIM ,  HYOUNMIN BAEK ,  JEONG-HO LEE ,  YOUNGWOO CHUNG ,  HEEGEUN JEONG

IPC: H01L27/146

Abstract: An image sensor includes; a substrate having a first surface and an opposing second surface and including unit pixels respectively having photoelectric conversion regions, a semiconductor pattern disposed in a first trench defining the unit pixels, the semiconductor pattern including a first semiconductor layer provided on an inner surface of the first trench and a second semiconductor layer provided on the first semiconductor layer, and a first contact provided on the second surface and connected to the semiconductor pattern. A height of the first semiconductor layer from a bottom surface of the first trench is less than a height of the second semiconductor layer from the bottom surface of the first trench.

公开(公告)号：US20200219912A1

公开(公告)日：2020-07-09

申请号：US16701750

申请日：2019-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： IN HO RO ,  DOOWON KWON ,  SEOKJIN KWON ,  JAMEYUNG KIM ,  JINYOUNG KIM ,  SUNGKI MIN ,  KWANSIK CHO ,  MANGEUN CHO ,  HO-CHUL JI

IPC: H01L27/146

Abstract: An image sensor including a semiconductor substrate having a first surface and a second surface, and a pixel region having a photoelectric conversion region; a first conductive pattern in a first trench defining the pixel region and extending from the first surface toward the second surface; a second conductive pattern in a second trench shallower than the first trench and defined between a plurality of active patterns on the first surface of the pixel region; a transfer transistor and a plurality of logic transistors on the active patterns; and a conductive line on the second surface and electrically connected to the first conductive pattern.