Fingerprint sensor package and smartcard including the same

    公开(公告)号:US11538268B2

    公开(公告)日:2022-12-27

    申请号:US17500434

    申请日:2021-10-13

    Abstract: A fingerprint sensor package includes a package substrate including an upper surface in which a sensing region and a peripheral region surrounding the sensing region are defined, and a lower surface facing the upper surface; a plurality of first sensing patterns located are arranged in the sensing region, are apart from each other in a first direction, and extend in a second direction crossing the first direction; a plurality of second sensing patterns that are arranged in the sensing region, are apart from each other in the second direction, and extend in the first direction; a coating member covering the sensing region; an upper ground pattern in the peripheral region and apart from the coating member to surround the coating member in the first and second directions; and a controller chip on the lower surface of the package substrate; and a plurality of capacitors.

    Semiconductor package including multiple semiconductor chips

    公开(公告)号:US11205631B2

    公开(公告)日:2021-12-21

    申请号:US16822300

    申请日:2020-03-18

    Abstract: Provided is a semiconductor package including a package structure including a base connection member including a redistribution layer, a first semiconductor chip including a plurality of first connection pads connected to the redistribution layer, an encapsulant disposed on the base connection member and covering at least a portion of the first semiconductor chip, and a backside connection member disposed on the encapsulant and including a backside wiring layer electrically connected to the redistribution layer, and a second semiconductor chip disposed on the base connection member or the backside connection member, the second semiconductor chip including a plurality of second connection pads connected to the redistribution layer or the backside wiring layer, the second semiconductor chip including a logic circuit, the first semiconductor chip including a logic input and output terminals that are connected to the logic circuit through at least one of the redistribution layer and the backside wiring layer.

    Semiconductor device including standard cells

    公开(公告)号:US12165701B2

    公开(公告)日:2024-12-10

    申请号:US17824464

    申请日:2022-05-25

    Abstract: A semiconductor device includes a first memory column group including a plurality of memory columns in which a plurality of bit cells are disposed; and a first peripheral column group including a plurality of peripheral columns in which a plurality of standard cells are disposed, wherein the plurality of standard cells are configured to perform an operation of reading/writing data from/to the plurality of bit cells through a plurality of bit lines, wherein the first memory column group and the first peripheral column group correspond to each other in a column direction, and wherein at least one of the plurality of peripheral columns has a cell height different from cell heights of the other peripheral columns, the cell height being measured in a row direction in which a gate line is extended.

    Fingerprint sensor package and smart card including fingerprint sensor package

    公开(公告)号:US11954938B2

    公开(公告)日:2024-04-09

    申请号:US18131133

    申请日:2023-04-05

    CPC classification number: G06V40/1306 G06K19/07354 G06K19/07747

    Abstract: A fingerprint sensor package includes a first substrate having a core insulating layer with a first surface and a second surface, and a through-hole passing through the first surface and the second surface, a first bonding pad disposed on the second surface of the core insulating layer, and an external connection pad, a second substrate disposed in the through-hole of the core insulating layer and including a plurality of first sensing patterns, a plurality of second sensing patterns, and a second bonding pad, a conductive wire connecting the first bonding pad and the second bonding pad to each other, a controller chip disposed on the second substrate, and a molding layer disposed on the second surface of the core insulating layer, filling the through-hole, covering the second substrate and the first bonding pad, and spaced apart from the external connection pad.

Patent Agency Ranking