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公开(公告)号:US20240105703A1
公开(公告)日:2024-03-28
申请号:US18322795
申请日:2023-05-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jaehyun Lim , Kwangjin Lee , Hyunjong Moon , Inho Choi
IPC: H01L25/18 , G06K19/073 , G06V40/13 , H01L23/00 , H01L23/538 , H01L25/00
CPC classification number: H01L25/18 , G06K19/07354 , G06V40/1306 , G06V40/1329 , H01L23/5388 , H01L24/37 , H01L24/40 , H01L24/41 , H01L25/50 , H01L24/16 , H01L24/73 , H01L24/84 , H01L2224/16145 , H01L2224/37013 , H01L2224/37124 , H01L2224/37147 , H01L2224/40101 , H01L2224/40106 , H01L2224/40157 , H01L2224/40499 , H01L2224/4103 , H01L2224/41051 , H01L2224/41176 , H01L2224/73205 , H01L2224/84005 , H01L2924/01039 , H01L2924/0665
Abstract: A fingerprint sensor package includes: a first substrate including a core insulating layer including a first surface and a second surface and a through-hole, a first bonding pad on the second surface, and an external connection pad between an edge of the second surface and the first bonding pad; a second substrate in the through-hole and including a third surface and a fourth surface, and including first sensing patterns on the third surface, spaced apart in a first direction, and extending in a second direction, second sensing patterns spaced apart from each other in the second direction and extending in the first direction, and a second bonding pad on the fourth surface; a conductive support electrically connecting the first bonding pad and the second bonding pad and supporting the first substrate and the second substrate; a controller chip on the second substrate; and a molding layer on the second surface.
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公开(公告)号:US11538268B2
公开(公告)日:2022-12-27
申请号:US17500434
申请日:2021-10-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jaehyun Lim , Younghwan Park , Kwangjin Lee , Inho Choi , Hyuntaek Choi
IPC: G06V40/13
Abstract: A fingerprint sensor package includes a package substrate including an upper surface in which a sensing region and a peripheral region surrounding the sensing region are defined, and a lower surface facing the upper surface; a plurality of first sensing patterns located are arranged in the sensing region, are apart from each other in a first direction, and extend in a second direction crossing the first direction; a plurality of second sensing patterns that are arranged in the sensing region, are apart from each other in the second direction, and extend in the first direction; a coating member covering the sensing region; an upper ground pattern in the peripheral region and apart from the coating member to surround the coating member in the first and second directions; and a controller chip on the lower surface of the package substrate; and a plurality of capacitors.
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公开(公告)号:US09948301B2
公开(公告)日:2018-04-17
申请号:US15211459
申请日:2016-07-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sangwook Han , Thomas Byunghak Cho , Jaehyun Lim , Sung-Jun Lee , Joonhee Lee , Jongwon Choi
IPC: H03L5/00 , H03K19/0175 , H01L27/02
CPC classification number: H03K19/017509 , H01L27/0248
Abstract: An integrated circuit (IC), a method of testing the IC, and a method of manufacturing the IC are provided. The IC includes analog circuitry, digital circuitry, at least one first connector, and a switching unit operatively coupled with the at least one first connector and configured to, if a first signal is received, couple the analog circuitry and the at least one first connector, and, if a second signal is received, couple the digital circuitry and the at least one first connector.
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公开(公告)号:US11205631B2
公开(公告)日:2021-12-21
申请号:US16822300
申请日:2020-03-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Yonghoon Kim , Jaehyun Lim , Yuntae Lee , Sayoon Kang
IPC: H01L23/00 , H01L23/31 , H01L23/48 , H01L25/065
Abstract: Provided is a semiconductor package including a package structure including a base connection member including a redistribution layer, a first semiconductor chip including a plurality of first connection pads connected to the redistribution layer, an encapsulant disposed on the base connection member and covering at least a portion of the first semiconductor chip, and a backside connection member disposed on the encapsulant and including a backside wiring layer electrically connected to the redistribution layer, and a second semiconductor chip disposed on the base connection member or the backside connection member, the second semiconductor chip including a plurality of second connection pads connected to the redistribution layer or the backside wiring layer, the second semiconductor chip including a logic circuit, the first semiconductor chip including a logic input and output terminals that are connected to the logic circuit through at least one of the redistribution layer and the backside wiring layer.
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公开(公告)号:US12165701B2
公开(公告)日:2024-12-10
申请号:US17824464
申请日:2022-05-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jaehyun Lim , Taehyung Kim , Sangshin Han
IPC: G11C11/41 , G11C11/419 , H01L27/02 , H10B10/00
Abstract: A semiconductor device includes a first memory column group including a plurality of memory columns in which a plurality of bit cells are disposed; and a first peripheral column group including a plurality of peripheral columns in which a plurality of standard cells are disposed, wherein the plurality of standard cells are configured to perform an operation of reading/writing data from/to the plurality of bit cells through a plurality of bit lines, wherein the first memory column group and the first peripheral column group correspond to each other in a column direction, and wherein at least one of the plurality of peripheral columns has a cell height different from cell heights of the other peripheral columns, the cell height being measured in a row direction in which a gate line is extended.
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公开(公告)号:US11954938B2
公开(公告)日:2024-04-09
申请号:US18131133
申请日:2023-04-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Gwangjin Lee , Jaehyun Lim , Heeyoub Kang , Hyunjong Moon , Yun Seok Choi , Inho Choi
IPC: G06V40/13 , G06K19/073 , G06K19/077
CPC classification number: G06V40/1306 , G06K19/07354 , G06K19/07747
Abstract: A fingerprint sensor package includes a first substrate having a core insulating layer with a first surface and a second surface, and a through-hole passing through the first surface and the second surface, a first bonding pad disposed on the second surface of the core insulating layer, and an external connection pad, a second substrate disposed in the through-hole of the core insulating layer and including a plurality of first sensing patterns, a plurality of second sensing patterns, and a second bonding pad, a conductive wire connecting the first bonding pad and the second bonding pad to each other, a controller chip disposed on the second substrate, and a molding layer disposed on the second surface of the core insulating layer, filling the through-hole, covering the second substrate and the first bonding pad, and spaced apart from the external connection pad.
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公开(公告)号:US11900709B2
公开(公告)日:2024-02-13
申请号:US17514088
申请日:2021-10-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jaehyun Lim , Younghwan Park , Kwangjin Lee , Dongha Lee , Hyuntaek Choi
IPC: H01L23/498 , H01L23/31 , H01L23/00 , G06K9/00 , G06V40/12 , G06K19/07 , G06K19/073 , G06K19/077
CPC classification number: G06V40/12 , G06K19/0718 , G06K19/07354 , G06K19/07747 , H01L23/3121 , H01L2224/16227
Abstract: A fingerprint sensor package includes a first substrate including a core insulating layer; a first bonding pad on the core insulating layer; and an external connection pad between an edge of the second surface of the core insulating layer and the first bonding pad, a second substrate on the core insulating layer, the second substrate including: a plurality of first sensing patterns spaced apart in a first direction and extending in a second direction intersecting with the first direction; a plurality of second sensing patterns spaced apart from each other in the second direction and extending in the first direction; and a second bonding pad, a conductive wire connecting the first bonding pad to the second bonding pad; a controller chip on the second substrate; and a molding layer covering the second substrate and the first bonding pad and spaced apart from the external connection pad.
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