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公开(公告)号:US20210193678A1
公开(公告)日:2021-06-24
申请号:US16926045
申请日:2020-07-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jiye Noh , Jinsoo Lim , Daehyun Jang , Jisung Cheon , Sangjun Hong
IPC: H01L27/11582 , H01L27/11565 , H01L23/48 , H01L23/528
Abstract: A semiconductor device includes a peripheral circuit structure disposed on a substrate; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack, the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.
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公开(公告)号:US11672119B2
公开(公告)日:2023-06-06
申请号:US17028029
申请日:2020-09-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jisung Cheon , Jiye Noh , Byunggon Park , Jinsoo Lim
IPC: H01L29/788 , H01L27/11582 , G11C7/18 , H01L23/522 , H01L27/11565
CPC classification number: H01L27/11582 , G11C7/18 , H01L23/5226 , H01L27/11565
Abstract: A vertical memory device includes a gate electrode structure, channels, a charge storage structure, and a division pattern. The gate electrode includes gate electrodes spaced apart from each other in a first direction. The channel extends through the gate electrode structure, and includes a first portion and a second portion on and contacting the first portion. The second portion includes a lower surface having a width less than that of an upper surface of the first portion. The charge storage structure covers an outer sidewall of the channel. The division pattern extends between the channels in a second direction, and includes a first dummy channel and a first dummy charge storage structure covering a sidewall and a lower surface thereof. The first dummy channel includes the same material as that the channel, and the first dummy charge storage structure includes the same material as the charge storage structure.
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公开(公告)号:US12010849B2
公开(公告)日:2024-06-11
申请号:US17934959
申请日:2022-09-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jiye Noh , Jinsoo Lim , Daehyun Jang , Jisung Cheon , Sangjun Hong
IPC: H10B43/27 , H01L21/762 , H01L23/48 , H01L23/528 , H10B41/10 , H10B41/35 , H10B41/41 , H10B41/49 , H10B43/10 , H10B43/40
CPC classification number: H10B43/27 , H01L23/481 , H01L23/528 , H10B43/10 , H10B43/40
Abstract: A semiconductor device includes a peripheral circuit structure; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.
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公开(公告)号:US20230032392A1
公开(公告)日:2023-02-02
申请号:US17934959
申请日:2022-09-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jiye Noh , Jinsoo Lim , Daehyun Jang , Jisung Cheon , Sangjun Hong
IPC: H01L27/11582 , H01L27/11565 , H01L23/528 , H01L23/48
Abstract: A semiconductor device includes a peripheral circuit structure; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.
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公开(公告)号:US11456316B2
公开(公告)日:2022-09-27
申请号:US16926045
申请日:2020-07-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jiye Noh , Jinsoo Lim , Daehyun Jang , Jisung Cheon , Sangjun Hong
IPC: H01L27/11582 , H01L23/48 , H01L23/528 , H01L27/11573 , H01L27/11519 , H01L27/11565
Abstract: A semiconductor device includes a peripheral circuit structure disposed on a substrate; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack, the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.
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