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    Semiconductor devices
    1.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11515322B2

    公开(公告)日：2022-11-29

    申请号：US16890500

    申请日：2020-06-02

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Seogoo Kang ,  Daehyun Jang ,  Jaeryong Sim ,  Jongseon Ahn ,  Jeehoon Han

    IPC分类号： H01L27/11582 ,  H01L27/11575 ,  H01L27/11548 ,  H01L27/11556

    摘要： A semiconductor device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate; and a memory cell region including a second substrate on an upper portion of the first substrate, gate electrodes spaced apart from each other and vertically stacked on the second substrate, channel structures extending vertically through the gate electrodes to the second substrate, first separation regions penetrating through the gate electrodes between the channel structures and extending in one direction, and a second separation region extending vertically to penetrate through the second substrate from above and having a bent portion due to a change in width.

    Methods of forming a semiconductor device
    3.
    发明授权
    Methods of forming a semiconductor device 有权
    形成半导体器件的方法

    公开(公告)号：US08980731B2

    公开(公告)日：2015-03-17

    申请号：US13724632

    申请日：2012-12-21

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jung Ho Kim ,  Sunghae Lee ,  Hanvit Yang ,  Dongwoo Kim ,  Chaeho Kim ,  Daehyun Jang ,  Ju-Eun Kim ,  Yong-Hoon Son ,  Sangryol Yang ,  Myoungbum Lee ,  Kihyun Hwang

    IPC分类号： H01L21/04 ,  H01L21/82 ,  H01L21/336 ,  H01L21/3205 ,  H01L29/76 ,  H01L29/792 ,  H01L27/115 ,  H01L29/66

    CPC分类号： H01L21/04 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    摘要： Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.

    摘要翻译： 提供了形成半导体器件的方法。 所述方法可以包括形成在衬底上交替和重复堆叠的第一和第二层，以及形成穿透第一层和第二层的开口。 所述方法还可以包括在开口中形成第一半导体图案。 所述方法还可以包括在第一半导体图案上形成绝缘图案。 所述方法还可以包括在绝缘图案上形成第二半导体图案。 所述方法还可以包括在第一半导体图案中提供掺杂剂。 此外，所述方法可以包括热处理第一半导体图案的一部分以形成第三半导体图案。

    METHOD OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    METHOD OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190288001A1

    公开(公告)日：2019-09-19

    申请号：US16180609

    申请日：2018-11-05

    申请人： Samsung Electronics Co., Ltd.

    发明人： Han Geun Yu ,  Daehyun Jang

    IPC分类号： H01L27/11582 ,  H01L21/033 ,  H01L21/311 ,  H01L27/11568 ,  H01L27/11565

    摘要： Methods of fabricating a three-dimensional semiconductor memory device are provided. A method may include forming a mold structure on a substrate including channel regions and a non-channel region between the channel regions, and forming, on the mold structure, a multilayered mask layer including a first mask layer, an etch stop layer, and a second mask layer that are sequentially stacked. The multilayered mask layer may include mask holes exposing the mold structure in the channel regions, dummy mask holes exposing the first mask layer in the non-channel region, and buffer spacers covering sidewalls of the second mask layer exposed by the mask holes and the dummy mask holes. The method may include etching the mold structure using the multilayered mask layer as an etch mask to form channel holes in the channel regions.

    Method of fabricating three-dimensional semiconductor memory device
    7.
    发明授权
    Method of fabricating three-dimensional semiconductor memory device 有权

    公开(公告)号：US11521983B2

    公开(公告)日：2022-12-06

    申请号：US16863381

    申请日：2020-04-30

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Han Geun Yu ,  Daehyun Jang

    IPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L21/033 ,  H01L21/311 ,  H01L29/10 ,  H01L21/02

    摘要： Methods of fabricating a three-dimensional semiconductor memory device are provided. A method may include forming a mold structure on a substrate including channel regions and a non-channel region between the channel regions, and forming, on the mold structure, a multilayered mask layer including a first mask layer, an etch stop layer, and a second mask layer that are sequentially stacked. The multilayered mask layer may include mask holes exposing the mold structure in the channel regions, dummy mask holes exposing the first mask layer in the non-channel region, and buffer spacers covering sidewalls of the second mask layer exposed by the mask holes and the dummy mask holes. The method may include etching the mold structure using the multilayered mask layer as an etch mask to form channel holes in the channel regions.

    SEMICONDUCTOR DEVICE HAVING WORD LINE SEPARATION LAYER
    8.
    发明申请
    SEMICONDUCTOR DEVICE HAVING WORD LINE SEPARATION LAYER 有权

    公开(公告)号：US20210193678A1

    公开(公告)日：2021-06-24

    申请号：US16926045

    申请日：2020-07-10

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Jiye Noh ,  Jinsoo Lim ,  Daehyun Jang ,  Jisung Cheon ,  Sangjun Hong

    IPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L23/48 ,  H01L23/528

    摘要： A semiconductor device includes a peripheral circuit structure disposed on a substrate; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack, the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.

    Three-dimensional semiconductor memory devices and methods of fabricating the same
    9.
    发明授权
    Three-dimensional semiconductor memory devices and methods of fabricating the same 有权

    公开(公告)号：US10971516B2

    公开(公告)日：2021-04-06

    申请号：US16294425

    申请日：2019-03-06

    申请人： Samsung Electronics Co., Ltd.

    发明人： Sung-Soo Ahn ,  Yong-Hoon Son ,  Minhyuk Kim ,  Jae Ho Min ,  Daehyun Jang

    IPC分类号： H01L27/11582 ,  H01L21/28 ,  H01L27/11565 ,  H01L21/311 ,  H01L27/1157

    摘要： Integrated circuit devices and methods of forming the same are provided. The devices may include a substrate including a cell region and an extension region and conductive layers stacked on the cell region in a vertical direction. The conductive layers may extend onto the extension region and may have a stair-step structure on the extension region. The devices may also include vertical structures on the substrate. Each of the vertical structures may extend in the vertical direction, and the vertical structures may include a first vertical structure on the cell region and a second vertical structure on the extension region. The first vertical structure may extend through the conductive layers and may include a first channel layer, the second vertical structure may be in the stair-step structure and may include a second channel layer, and the second channel layer may be spaced apart from the substrate in the vertical direction.

    Shrouds and substrate treating systems including the same
    10.
    发明授权
    Shrouds and substrate treating systems including the same 有权

    公开(公告)号：US10950419B2

    公开(公告)日：2021-03-16

    申请号：US15945001

    申请日：2018-04-04

    申请人： Samsung Electronics Co., Ltd.

    发明人： Edward Sung ,  Hyuk Kim ,  Daehyun Jang ,  Sung Il Cho

    IPC分类号： H01J37/32 ,  H01L21/67 ,  H01L21/683

    摘要： Shrouds and substrate treating systems including the same are provided. Substrate treating systems may include a process chamber, a supporter, and a plasma source that is spaced apart from the supporter in a vertical direction. The substrate treating systems may also include a shroud configured to contain the plasma therein. The shroud may include a sidewall portion and a first flange portion extending horizontally from the sidewall portion and including a plurality of first slits that extend through a thickness of the first flange portion. The first flange portion may define a first opening, and a portion of the supporter may extend through the first opening. The sidewall portion may include a plurality of second slits, and each of the plurality of second slits may extend through a thickness of the sidewall portion and may extend from one of the plurality of first slits toward the plasma source.