公开(公告)号：US10535395B2

公开(公告)日：2020-01-14

申请号：US15599819

申请日：2017-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo-Ho Cha ,  Chankyung Kim ,  Sungchul Park ,  Kwangchol Choe

IPC: G11C7/00 ,  G11C11/408 ,  G06F12/02 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: Disclosed is a memory device which includes a first memory cell connected to a word line and a first bit line, a second memory cell connected to the word line and a second bit line, and a row decoder selecting the word line, a row decoder configured to select the word line, and a column decoder. A first distance between the row decoder and the first memory cell is shorter than a second distance between the row decoder and the second memory cell. The column decoder selects the first bit line based on a time point when the first memory cell is activated.

公开(公告)号：US09972371B2

公开(公告)日：2018-05-15

申请号：US15596558

申请日：2017-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo-Ho Cha ,  Chankyung Kim ,  Sungchul Park ,  Hoyoung Song ,  Kwangchol Choe

IPC: G11C7/12 ,  G11C7/06 ,  G11C7/22 ,  G11C7/14

CPC classification number: G11C7/12 ,  G11C7/062 ,  G11C7/065 ,  G11C7/14 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099

Abstract: A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.

公开(公告)号：US20230186960A1

公开(公告)日：2023-06-15

申请号：US17852593

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hijung Kim ,  Kwangchol Choe ,  Kwangsook Noh ,  Jaepil Lee

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/12 ,  G11C8/14 ,  H03K19/017

CPC classification number: G11C7/222 ,  G11C7/12 ,  G11C7/1039 ,  G11C8/14 ,  H03K19/01742

Abstract: A memory device includes a memory cell array having memory cells connected to wordlines and bitlines, and a clock buffer receiving a clock signal for performing a read operation or a write operation on at least one of the memory cells. The clock buffer includes a plurality of serially connected clock repeaters, and the plurality of clock repeaters have at least one pair of clock repeaters having different imbalanced driving capabilities.

公开(公告)号：US10332571B2

公开(公告)日：2019-06-25

申请号：US15951554

申请日：2018-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo-Ho Cha ,  Chankyung Kim ,  Sungchul Park ,  Hoyoung Song ,  Kwangchol Choe

IPC: G11C11/56 ,  G11C7/12 ,  G11C7/06 ,  G11C7/14 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099

Abstract: A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.

公开(公告)号：US12237048B2

公开(公告)日：2025-02-25

申请号：US17852593

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hijung Kim ,  Kwangchol Choe ,  Kwangsook Noh ,  Jaepil Lee

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/12 ,  G11C8/14 ,  H03K19/017

Abstract: A memory device includes a memory cell array having memory cells connected to wordlines and bitlines, and a clock buffer receiving a clock signal for performing a read operation or a write operation on at least one of the memory cells. The clock buffer includes a plurality of serially connected clock repeaters, and the plurality of clock repeaters have at least one pair of clock repeaters having different imbalanced driving capabilities.

公开(公告)号：US20180233183A1

公开(公告)日：2018-08-16

申请号：US15951554

申请日：2018-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo-Ho Cha ,  Chankyung Kim ,  Sungchul Park ,  Hoyoung Song ,  Kwangchol Choe

IPC: G11C7/12 ,  G11C11/4094 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4099 ,  G11C7/06 ,  G11C7/14

CPC classification number: G11C7/12 ,  G11C7/062 ,  G11C7/065 ,  G11C7/14 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/565

Abstract: A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.