公开(公告)号：US20220207227A1

公开(公告)日：2022-06-30

申请号：US17486794

申请日：2021-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGJIN LEE ,  Yunkyoung Song ,  Dawoon Choi ,  Kyoil Koo

IPC: G06F30/392 ,  H01L21/308 ,  G03F7/20

Abstract: A method for detecting a stochastic weak point of a layout pattern of a semiconductor integrated circuit includes: forming a semiconductor integrated circuit by exposing a wafer which is masked by a layout pattern and coated with a photoresist to light, and etching the circuit according to the layout pattern, calculating line edge roughness (LER) of the circuit, and calculating a variability constant for fitting the line edge roughness to a normal distribution from a polymer concentration value of the photoresist. The polymer concentration value is calculated from modeling the layout pattern, a total value of intensity of light reaching the photoresist, and an intensity value of light reaching one point of the photoresist. The method further includes calculating a probability distribution of the polymer concentration value of the layout pattern based on the variability constant, and calculating a stochastic weak point of the layout pattern from the probability distribution.

公开(公告)号：US11977828B2

公开(公告)日：2024-05-07

申请号：US17486794

申请日：2021-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjin Lee ,  Yunkyoung Song ,  Dawoon Choi ,  Kyoil Koo

IPC: G06F30/392 ,  G03F7/00 ,  H01L21/308 ,  G06F111/08 ,  G06F111/10

CPC classification number: G06F30/392 ,  G03F7/70033 ,  G03F7/70625 ,  G03F7/7065 ,  H01L21/308 ,  G06F2111/08 ,  G06F2111/10

Abstract: A method for detecting a stochastic weak point of a layout pattern of a semiconductor integrated circuit includes: forming a semiconductor integrated circuit by exposing a wafer which is masked by a layout pattern and coated with a photoresist to light, and etching the circuit according to the layout pattern, calculating line edge roughness (LER) of the circuit, and calculating a variability constant for fitting the line edge roughness to a normal distribution from a polymer concentration value of the photoresist. The polymer concentration value is calculated from modeling the layout pattern, a total value of intensity of light reaching the photoresist, and an intensity value of light reaching one point of the photoresist. The method further includes calculating a probability distribution of the polymer concentration value of the layout pattern based on the variability constant, and calculating a stochastic weak point of the layout pattern from the probability distribution.

公开(公告)号：US10431593B2

公开(公告)日：2019-10-01

申请号：US15860082

申请日：2018-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn Yun ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Kyoil Koo ,  Hoosung Cho ,  Sunyoung Kim ,  Cheol Ryou ,  Jaesun Yun

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/1157

Abstract: Disclosed is a three-dimensional semiconductor memory device that includes first to third channel groups arranged in a first direction on a substrate. The first to third channel groups are spaced apart from each other along a second direction on the substrate. Each of the first to third channel groups includes a plurality of vertical channels that extend in a third direction perpendicular to a top surface of the substrate. The first and second channel groups are adjacent to each other in the second direction and spaced apart at a first distance in the second direction. The second and third channel groups are adjacent to each other in the second direction and are spaced apart at a second distance that is less than the first distance.