公开(公告)号：US20250142929A1

公开(公告)日：2025-05-01

申请号：US18666120

申请日：2024-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungbin CHUN ,  Gyeom KIM ,  Ryong HA

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/167 ,  H01L29/66

Abstract: A semiconductor device includes a substrate; an active pattern on the substrate; a plurality of channel layers stacked on the active pattern to be spaced apart from each other; a gate structure surrounding the plurality of channel layers; source/drain patterns including a first epitaxial layer disposed along side surfaces of the plurality of channel layers on a portion of the active pattern and a second epitaxial layer disposed on the first epitaxial layer and having a trench; contact structures disposed on the source/drain patterns, respectively, and including a first extension portion filling the trench, and a pair of second extension portions extending along both side surfaces of the source/drain patterns in the second direction, respectively; and a metal-semiconductor compound layer disposed between the source/drain patterns and the contact structures.

公开(公告)号：US20240038842A1

公开(公告)日：2024-02-01

申请号：US18119037

申请日：2023-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungbin CHUN ,  Gyeom KIM ,  Dahye KIM ,  Youngkwang KIM ,  Jinbum KIM

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66439

Abstract: An integrated circuit (IC) device includes a fin-type active region on a substrate, a pair of nanosheets on the fin-type active region, a gate line surrounding the pair of nanosheets, the gate line including a sub-gate portion between the pair of nanosheets, a source/drain region contacting the pair of nanosheets, and a gate dielectric film between the gate line and the pair of nanosheets and between the gate line and the source/drain region, wherein the source/drain region includes a first blocking layer between the pair of nanosheets, the first blocking layer including an edge barrier enhancing portion facing the sub-gate portion, and a second blocking layer, wherein the first blocking layer includes a portion that intermittently extends in the vertical direction.

公开(公告)号：US20240006503A1

公开(公告)日：2024-01-04

申请号：US18128417

申请日：2023-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyeom KIM ,  Jinbum KIM ,  Dahye KIM ,  Kyungbin CHUN

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/0673

Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate including an active region; a gate structure intersecting the active region on the substrate; channel layers on the active region, spaced apart from each other and surrounded by the gate structure; and a source/drain region on the active region adjacent the gate structure and connected to the plurality of channel layers. The source/drain region includes: a first semiconductor layer on side surfaces of the channel layers; a diffusion barrier layer on an upper region of the first semiconductor layer and including carbon, wherein an upper surface of a first channel layer that is a lowermost channel layer among the plurality of channel layers is provided between the substrate and a lower end of the diffusion barrier layer; and a second semiconductor layer on the diffusion barrier layer and the first semiconductor layer.

公开(公告)号：US20230268395A1

公开(公告)日：2023-08-24

申请号：US18062713

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum KIM ,  Sujin JUNG ,  Gyeom KIM ,  Dahye KIM ,  Ingyu JANG ,  Kyungbin CHUN

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/764 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/764 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/66439

Abstract: A semiconductor device includes; a gate structure intersecting an active region, and a plurality of channel layers, extending on the substrate in a second direction, and surrounding the plurality of channel layers; a source/drain region contacting the plurality of channel layers on at least one side of the gate structure and including a first semiconductor material with first impurities having a first conductivity type; and a lower structure in contact with the active region and below the source/drain region. The lower structure includes a first layer disposed on the active region and including an insulating material; a second layer disposed on the first layer and including a second semiconductor material; with an air gap defined by the first layer and the second layer, wherein the second semiconductor material of the second layer has no conductivity type or has a second conductivity type different from the first conductivity type.