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    INTEGRATED CIRCUIT DEVICE
    2.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20220238666A1

    公开(公告)日：2022-07-28

    申请号：US17404078

    申请日：2021-08-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dohee KIM ,  Gyeom KIM ,  Jinbum KIM ,  Jaemun KIM ,  Seunghun LEE

    IPC: H01L29/417 ,  H01L29/78 ,  H01L27/088

    Abstract: An integrated circuit (IC) device includes a fin-type active region extending in a first lateral direction on a substrate, a gate line extending in a second lateral direction on the fin-type active region, an insulating spacer covering a sidewall of the gate line, a source/drain region at a position adjacent to the gate line, a metal silicide film covering a top surface of the source/drain region, and a source/drain contact apart from the gate line with the insulating spacer therebetween in the first lateral direction. The source/drain contact includes a bottom contact segment being in contact with a top surface of the metal silicide film and an upper contact segment integrally connected to the bottom contact segment. A width of the bottom contact segment is greater than a width of at least a portion of the upper contact segment in the first lateral direction.

    SEMICONDUCTOR DEVICE INCLUDING ACTIVE REGION AND GATE STRUCTURE
    3.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING ACTIVE REGION AND GATE STRUCTURE 有权

    公开(公告)号：US20220231159A1

    公开(公告)日：2022-07-21

    申请号：US17716005

    申请日：2022-04-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joohee JUNG ,  Jinbum KIM ,  Dongil BAE

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L27/088

    Abstract: A semiconductor device includes an active region extending from a substrate in a vertical direction, source/drain regions spaced apart from each other on the active region, a fin structure between the source/drain regions on the active region, the fin structure including a lower semiconductor region on the active region, a stack structure having alternating first and second semiconductor layers on the lower semiconductor region, a side surface of at least one of the first semiconductor layers being recessed, and a semiconductor capping layer on the stack structure, an isolation layer covering a side surface of the active region, a gate structure overlapping the fin structure and covering upper and side surfaces of the fin structure, the semiconductor capping layer being between the gate structure and each of the lower semiconductor region and stack structure, and contact plugs electrically connected to the source/drain regions.

    SEMICONDUCTOR MEMORY DEVICE INCLUDING A VERTICAL CHANNEL TRANSISTOR
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE INCLUDING A VERTICAL CHANNEL TRANSISTOR 有权

    公开(公告)号：US20250048621A1

    公开(公告)日：2025-02-06

    申请号：US18641488

    申请日：2024-04-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunghwan JANG ,  Jinbum KIM ,  Hyojin PARK ,  Sunguk JANG

    IPC: H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    Abstract: A semiconductor memory device includes: a plurality of word lines extending in a first direction; a plurality of channel layers alternately arranged with the word lines, wherein the channel layers extend in a second direction; and a plurality of bit lines located on the word lines and the channel layers, and extending in a third direction. The bit lines are electrically connected to the channel layers. The plurality of word lines include: a plurality of selected word lines to which a positive voltage is applied; and a plurality of non-selected word lines to which a negative voltage is applied. The plurality of channel layers include: a selected channel layer that is turned on; and a non-selected channel layer that is turned off.

    SEMICONDUCTOR DEVICE
    6.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230411487A1

    公开(公告)日：2023-12-21

    申请号：US18112122

    申请日：2023-02-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongjun NAM ,  Sangmoon LEE ,  Jinbum KIM ,  Hyojin KIM

    IPC: H01L29/49 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

    CPC classification number: H01L29/4908 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775

    Abstract: A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns, which are vertically stacked to be spaced apart from each other, a source/drain pattern connected to the plurality of semiconductor patterns, a gate electrode including a plurality of gate electrode portions, a gate electrode portion interposed between adjacent ones of the semiconductor patterns, and a plurality of barrier patterns each comprising an epitaxial layer including single-crystalline silicon oxide. ,A barrier pattern interposed between each of the adjacent ones of the semiconductor patterns and a respective gate electrode portion.

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230100189A1

    公开(公告)日：2023-03-30

    申请号：US17730928

    申请日：2022-04-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dahye KIM ,  Sujin JUNG ,  Ingyu JANG ,  Jinbum KIM

    IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417

    Abstract: A semiconductor device includes a fin-type active region that protrudes from a substrate and extends in a first direction, a plurality of channel layers on the fin-type active region that are spaced apart from each other in a second direction that is perpendicular to an upper surface of the substrate, a gate structure that intersects the fin-type active region, extends in the second direction, and surrounds each of the plurality of channel layers in a third direction, fence spacers on side surfaces of the fin-type active region in the second direction on sides of the gate structure and extending in the second direction, and a source/drain region between the fence spacers on the fin-type active region at sides of the gate structure, connected to each of the plurality of channel layers, and having voids in side surfaces adjacent the fence spacers.

    SEMICONDUCTOR DEVICES
    8.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220069134A1

    公开(公告)日：2022-03-03

    申请号：US17206229

    申请日：2021-03-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dongwoo KIM ,  Jinbum KIM ,  Gyeom KIM ,  Dohee KIM ,  Seunghun LEE

    IPC: H01L29/786 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/417 ,  H01L21/02 ,  H01L29/66

    Abstract: A semiconductor device including an active region extending in a first direction on a substrate; channel layers vertically spaced apart on the active region; a gate structure extending in a second direction and intersecting the active region, the gate structure surrounding the channel layers; a source/drain region on the active region in contact with the channel layers; and a contact plug connected to the source/drain region, wherein the source/drain region includes a first epitaxial layer on side surfaces of the channel layers and including a first impurity; a second epitaxial layer on the first epitaxial layer and including the first impurity and a second impurity; and a third epitaxial layer on the second epitaxial layer and including the first impurity, and in a horizontal sectional view, the second epitaxial layer includes a peripheral portion having a thickness in the first direction that increases along the second direction.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250098147A1

    公开(公告)日：2025-03-20

    申请号：US18828170

    申请日：2024-09-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunghwan JANG ,  Wonhee CHOI ,  Jinbum KIM ,  Daejin NAM ,  Hyojin PARK ,  Sunguk JANG

    IPC: H10B12/00

    Abstract: A semiconductor device includes a substrate, a bit line extending in a first direction on the substrate, a first vertical channel pattern and a second vertical channel pattern on the bit line, a back gate electrode between the first vertical channel pattern and the second vertical channel pattern and extending in a second direction perpendicular to the first direction across the bit line, a first word line extending in the second direction from one side of the first vertical channel pattern, a second word line extending in the second direction from other side of the second vertical channel pattern, and a contact pattern connected to each of the first vertical channel pattern and the second vertical channel pattern. When viewed from a cross-sectional view, each of the first vertical channel pattern and the second vertical channel pattern have a trapezoidal shape with the long sides facing each other.

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