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    Semiconductor device having buried gate structure and method of fabricating the same
    1.
    发明授权
    Semiconductor device having buried gate structure and method of fabricating the same 有权
    具有掩埋栅极结构的半导体器件及其制造方法

    公开(公告)号：US09437697B2

    公开(公告)日：2016-09-06

    申请号：US14551857

    申请日：2014-11-24

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Min-Hee Cho

    IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/49

    CPC分类号： H01L27/10823 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/423 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7831

    摘要： A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.

    摘要翻译： 半导体器件包括限定衬底中的有源区的器件隔离区和掩埋在衬底的有源区中的栅结构。 栅极结构中的至少一个包括栅极沟槽，保形地形成在栅极沟槽的内壁上的栅极绝缘层，保形地形成在栅极绝缘层上的栅极阻挡图案，栅极绝缘层设置在栅极沟槽的下部，栅极 形成在栅极阻挡图案上并填充栅极沟槽的下部的电极图案，保形地形成在栅极绝缘层上的电极保护层，栅极绝缘层设置在栅极沟槽的上部以与栅极阻挡图案和栅极接触 电极图案，保形地形成在电极保护层上的缓冲氧化物层，以及形成在缓冲氧化物层上以填充栅极沟槽的上部的栅极覆盖绝缘层。

    Semiconductor device having buried gate structure and method of fabricating the same
    2.
    发明授权
    Semiconductor device having buried gate structure and method of fabricating the same 有权

    公开(公告)号：US10249628B2

    公开(公告)日：2019-04-02

    申请号：US15865467

    申请日：2018-01-09

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Min-Hee Cho

    IPC分类号： H01L29/02 ,  H01L27/108 ,  H01L29/423 ,  H01L29/78 ,  H01L29/49

    摘要： A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.

    Semiconductor devices
    3.
    发明授权
    Semiconductor devices 有权
    半导体器件

    公开(公告)号：US09425297B2

    公开(公告)日：2016-08-23

    申请号：US14698504

    申请日：2015-04-28

    申请人： Samsung Electronics Co., Ltd.

    发明人： Min-Hee Cho

    IPC分类号： H01L29/66 ,  H01L29/165 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L27/12

    CPC分类号： H01L29/66977 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/785

    摘要： Semiconductor devices include an intrinsic semiconductor region on a substrate, a source region adjacent to a first side surface of the semiconductor region and doped with a p-type dopant, a drain region adjacent to a second side surface of the semiconductor region, a gate electrode on the semiconductor region, a source gate electrode on the source region, and a drain gate electrode on the drain region. The second side surface is a reverse side of the first side surface. The drain region is doped with a p-type dopant.

    摘要翻译： 半导体器件包括衬底上的本征半导体区域，与半导体区域的第一侧表面相邻并且掺杂有p型掺杂剂的源极区域，与半导体区域的第二侧表面相邻的漏极区域，栅电极 在半导体区域上，源极区上的源极电极和漏极区域上的漏极栅电极。 第二侧面是第一侧面的背面。 漏区掺杂有p型掺杂剂。