MULTIPLEXER AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

    公开(公告)号:US20220166429A1

    公开(公告)日:2022-05-26

    申请号:US17387221

    申请日:2021-07-28

    Abstract: A multiplexer includes a charging circuit; a plurality of sampling switches receiving a plurality of input signals; and a plurality of boosting circuits connected between the sampling switches and the charging circuit and sharing the charging circuit. First and second charging switches of the charging circuit are controlled by a first clock signal. Each of the boosting circuits includes a first boosting switch connected to a first node of the charging circuit and a gate of one of the sampling switches, a second boosting switch connected between a second node of the charging circuit and the one sampling switch, and a level shifter configured to control the first boosting switch and the second boosting switch in response to a second clock signal and a selection signal.

    ELECTRONIC DEVICE WITH STRUCTURE FOR HARVESTING ENERGY

    公开(公告)号:US20210184601A1

    公开(公告)日:2021-06-17

    申请号:US17118899

    申请日:2020-12-11

    Abstract: An electronic device includes a housing structure including a first cover facing in a first direction and forming a first surface of the electronic device, and a second cover facing in a second direction opposite to the first direction and forming a second surface of the electronic device. The electronic device also includes a display positioned in a space formed by the housing structure and exposed through the first surface. The electronic device further includes an energy harvesting structure positioned in the space and configured to generate a current from a contact input to the first surface and a sound input generated inside and outside the electronic device. The electronic device additionally includes a battery positioned in the space. The electronic device also includes a charging circuit configured to charge the battery using the current received from the energy harvesting structure.

    CACHE MEMORY SYSTEM AND OPERATING METHOD THEREOF
    10.
    发明申请
    CACHE MEMORY SYSTEM AND OPERATING METHOD THEREOF 有权
    缓存记忆系统及其操作方法

    公开(公告)号:US20160077969A1

    公开(公告)日:2016-03-17

    申请号:US14692828

    申请日:2015-04-22

    Abstract: A cache memory apparatus includes a tag comparator configured to compare upper bits of each of pieces of tag data included in a set indicated by a set address that is received with upper bits of a tag address that is received, compare other bits of each of the pieces of the tag data with other bits of the tag address, and determine whether there is a cache hit or a cache miss based on results of the comparisons, and an update controller configured to, in response to the cache miss being determined, determine, as an update candidate, a piece among pieces of cache data included in the set and corresponding to the pieces of the tag data, based on the result of the comparison of the upper bits of each of the pieces of the tag data and the upper bits of the tag address, and update the update candidate with new data.

    Abstract translation: 高速缓冲存储器装置包括:标签比较器,被配置为比较由接收到的设定地址所指定的集合中包含的每个标签数据的高位,比较接收到的标签地址的高位, 标签数据与标签地址的其他位的片段,并且基于比较的结果来确定是否存在高速缓存命中或高速缓存未命中;以及更新控制器,被配置为响应于所确定的高速缓存未命中, 作为更新候选者,基于每个标签数据的高位和高位之间的比较结果,包括在集合中并与标签数据相对应的多条高速缓存数据中的一条 的标签地址,并用新数据更新更新候选。

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