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    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11557596B2

    公开(公告)日：2023-01-17

    申请号：US17192086

    申请日：2021-03-04

    申请人： Samsung Electronics Co., Ltd.

    发明人： Seoryong Park ,  Seunguk Han ,  Jiyoung Ahn ,  Kiseok Lee ,  Yoonyoung Choi ,  Jiseok Hong

    IPC分类号： H01L27/11551 ,  H01L27/11519 ,  G11C8/14 ,  H01L27/11578 ,  G11C7/18 ,  H01L27/11565

    摘要： A semiconductor memory device includes a substrate with a cell array region, a first interface region, and a second interface region, the cell array region being provided with active regions, bit lines on the cell array region and the second interface region, dielectric patterns on top surfaces of the bit lines and extending along the top surfaces of the bit lines and further extending onto the first interface region, a device isolation pattern on the substrate, and including a first portion on the cell array region and a second portion on the first interface region, the first portion defining the active regions, the second portion being provided with first recesses, and each first recess being disposed between two adjacent dielectric patterns, and first sacrificial semiconductor patterns disposed on the first interface region and in the first recesses. The first sacrificial semiconductor patterns include polycrystalline silicon.

    Semiconductor devices
    5.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11716839B2

    公开(公告)日：2023-08-01

    申请号：US17357139

    申请日：2021-06-24

    申请人： Samsung Electronics Co., Ltd.

    发明人： Joonkyu Rhee ,  Jiyoung Ahn ,  Hyunyong Kim ,  Jamin Koo ,  Yongseok Ahn ,  Minsub Um ,  Sangho Lee ,  Yoonyoung Choi

    IPC分类号： H10B12/00

    CPC分类号： H10B12/315 ,  H10B12/34

    摘要： A semiconductor device includes an active pattern on a substrate, a gate structure buried at an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure covering a lower sidewall of the bit line structure, a contact plug structure on the active pattern and adjacent to the bit line structure, and a capacitor on the contact plug structure. The lower spacer structure includes first and second lower spacers that are sequentially stacked from the lower sidewall of the bit line structure in a horizontal direction that is substantially parallel to an upper surface of the substrate, the first lower spacer includes an oxide, and contacts the lower sidewall of the bit line structure, but does not contact the contact plug structure, and the second lower spacer includes a material different from any of the materials of the first lower spacer.

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US12048143B2

    公开(公告)日：2024-07-23

    申请号：US17392775

    申请日：2021-08-03

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jiyoung Ahn ,  Yongseok Ahn ,  Hyunyong Kim ,  Minsub Um ,  Ju Hyung We ,  Joonkyu Rhee ,  Yoonyoung Choi

    IPC分类号： H10B12/00

    CPC分类号： H10B12/315 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485

    摘要： A semiconductor memory device includes a substrate including a device isolation pattern defining an active pattern extending in a first direction and including first and second source/drain regions, a word line extending in a second direction intersecting the first direction, a bit line that is on the word line and electrically connected to the first source/drain region and that extends in a third direction that intersects the first and second directions, a bit-line spacer on a sidewall of the bit line, a storage node contact electrically connected to the second source/drain region and spaced apart from the bit line across the bit-line spacer, and a dielectric pattern between the bit-line spacer and the storage node contact. The bit-line spacer includes a first spacer covering the sidewall of the bit line and a second spacer between the dielectric pattern and the first spacer.