公开(公告)号：US20230292630A1

公开(公告)日：2023-09-14

申请号：US17966183

申请日：2022-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Siyeon CHO ,  Taeyoung KIM ,  Hyunmog PARK ,  Bongyong LEE ,  Yukio HAYAKAWA

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  H01L43/10 ,  G11C11/16 ,  G11C11/18

CPC classification number: H01L43/04 ,  G11C11/161 ,  G11C11/18 ,  H01L27/222 ,  H01L43/06 ,  H01L43/10

Abstract: A magnetic memory device includes a loop-type magnetic track having a first part and a second part that are arranged in a counterclockwise direction, a first conductive line on a top surface of the first part, and a second conductive line on a bottom surface of the second part. The magnetic track includes a lower magnetic layer, a spacer layer, and an upper magnetic layer that are sequentially stacked. Each of the first and second conductive lines includes heavy metal. Each of the first and second conductive lines is configured to generate spin-orbit torque caused by current that flows therein. The spin-orbit torque causes magnetic domains in the magnetic track to move in a clockwise direction or in the counterclockwise direction.

公开(公告)号：US20240306398A1

公开(公告)日：2024-09-12

申请号：US18594350

申请日：2024-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongseok KIM ,  Yukio HAYAKAWA ,  Minjun LEE ,  Bongyong LEE ,  Siyeon CHO

IPC: H10B53/30 ,  H10B53/20

CPC classification number: H10B53/30 ,  H10B53/20

Abstract: A three-dimensional non-volatile memory device includes a plurality of horizontal word lines spaced apart from each other in a vertical direction, a pillar gate electrode buried in a first channel hole that passes through the horizontal word lines in the vertical direction, and a first dielectric layer disposed between the pillar gate electrode and the horizontal word lines in a cross section. The pillar gate electrode, the first dielectric layer, and the horizontal word lines correspond to memory cells including a plurality of variable capacitors spaced apart from each other in a vertical direction. The memory device further includes a selection transistor on the pillar gate electrode and the horizontal word lines and connected to one end of the pillar gate electrode, and a storage transistor under the pillar gate electrode and the horizontal word lines and connected to another end of the pillar gate electrode.

公开(公告)号：US20250024684A1

公开(公告)日：2025-01-16

申请号：US18672512

申请日：2024-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghyun PARK ,  Hyuncheol KIM ,  Suhwan LIM ,  Siyeon CHO

IPC: H10B51/20 ,  H10B51/30

Abstract: A vertical semiconductor device includes a substrate, a stacked structure including a plurality of insulation patterns and a plurality of gate electrode structures alternately and repeatedly stacked on the substrate in a vertical direction substantially perpendicular to a surface of the substrate, a channel pattern passing through the stacked structure, a gate insulation layer surrounding an outer wall of the channel pattern, and a gate insulation pattern disposed between the gate insulation layer and the gate electrode structures. The gate insulation layer includes a metal oxide having paraelectricity, and the gate insulation pattern has ferroelectricity. The gate insulation layer includes a first portion contacting one of the insulation patterns and a second portion contacting the gate insulation pattern.

公开(公告)号：US20240040797A1

公开(公告)日：2024-02-01

申请号：US18142291

申请日：2023-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunmook CHOI ,  Jihong KIM ,  Siyeon CHO

IPC: H10B51/30

CPC classification number: H10B51/30

Abstract: A three-dimensional non-volatile memory device includes horizontal word lines separated from each other in a vertical direction, horizontal ferroelectric layers arranged among the horizontal word lines, the horizontal ferroelectric layers including upper horizontal ferroelectric layers and lower horizontal ferroelectric layers, vertical ferroelectric layers contacting side walls of the horizontal ferroelectric layers and extending in the vertical direction, a semiconductor pillar passing through the horizontal word lines in the vertical direction, and a channel region between the horizontal word lines and the semiconductor pillar, wherein the upper horizontal ferroelectric layers and the lower horizontal ferroelectric layers are separated from each other by an air gap in the vertical direction.

公开(公告)号：US20230329012A1

公开(公告)日：2023-10-12

申请号：US18149929

申请日：2023-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongyong LEE ,  Taeyoung KIM ,  Hyunmog PARK ,  Siyeon CHO

IPC: H10B80/00 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B80/00 ,  H10B43/27 ,  H10B41/27

Abstract: A semiconductor device may include a first substrate structure including a substrate, circuit elements on the substrate, and first bonding layers on the circuit elements, and a second substrate structure on the first substrate structure. The second substrate structure may include a plate layer, an intermediate insulating layer below the plate layer and including silicon nitride, gate electrodes below the intermediate insulating layer and stacked to be spaced apart from each other in a vertical direction, a channel structure in a channel hole passing through the intermediate insulating layer and the gate electrodes and including a semiconductor layer, and second bonding layers connected to the first bonding layers. The channel hole may have a first width in a first portion passing through the gate electrodes and a second width, wider than the first width, in a second portion passing through the intermediate insulating layer.