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公开(公告)号：US20230206976A1
公开(公告)日：2023-06-29
申请号：US17875730
申请日：2022-07-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwan LEE , Yongseok KIM , Hyuncheol KIM , Jongman PARK , Dongsoo WOO , Minjun LEE
IPC: G11C11/22 , H01L27/11597 , H01L21/28
CPC classification number: G11C11/223 , G11C11/2255 , G11C11/2257 , H01L27/11597 , H01L29/40111
Abstract: A semiconductor device including a substrate; a stack including electrodes and a channel separation pattern, the electrodes being stacked on the substrate and spaced apart from each other, and the channel separation pattern being between adjacent electrodes; and a vertical structure penetrating the stack, wherein the vertical structure includes a conductive pillar, a channel structure, and an interposing layer between the conductive pillar and the channel structure, the channel structure includes first and second channel layers vertically spaced apart from each other by the channel separation pattern, the electrodes include first and second electrodes, which are connected to the first and second channel layers, the channel separation pattern is between the first channel layer and the second channel layer, and the channel separation pattern is between one second electrode that is connected to the first channel layer and one first electrode that is connected to the second channel layer.
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公开(公告)号：US20230140318A1
公开(公告)日：2023-05-04
申请号：US17875781
申请日：2022-07-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol KIM , Yongseok KIM , Dongsoo WOO , Kyunghwan LEE , Minjun LEE
IPC: H01L29/792 , H01L29/423 , G11C11/22 , G11C11/56
Abstract: A semiconductor memory device may include a substrate, first and second impurity regions on the substrate, first and second gate insulating layers sequentially stacked on the substrate and extended in a direction between the first and second impurity regions, and a gate electrode on the second gate insulating layer. The first and second impurity regions may have different conductivity types from each other, a bottom surface of the first gate insulating layer may be in direct contact with a top surface of the substrate, and the second gate insulating layer may include a ferroelectric material.
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公开(公告)号：US20230096214A1
公开(公告)日：2023-03-30
申请号：US17952637
申请日：2022-09-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghwan LEE , Yongseok KIM , Hyuncheol KIM , Jongman PARK , Dongsoo WOO , Minjun LEE
IPC: H01L27/1159 , H01L27/11597
Abstract: A semiconductor device includes a plurality of gate electrodes extending on a substrate in a first horizontal direction and each including first and second vertical extension sidewalls that are opposite to each other, a channel arranged on the first vertical extension sidewall of each gate electrode and including a vertical extension portion, a ferroelectric layer and a gate insulating layer that are sequentially located between the channel layer and the first vertical extension sidewall of each gate electrode, an insulating layer on the second vertical extension sidewall of each gate electrode, and a plurality of bit lines electrically connected to the channel layer and extending in a second horizontal direction that is different from the first horizontal direction.
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公开(公告)号：US20230011675A1
公开(公告)日：2023-01-12
申请号：US17683460
申请日：2022-03-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwan LEE , Yongseok KIM , Hyuncheol KIM , Jongman PARK , Dongsoo WOO
IPC: H01L27/11597 , H01L27/11587 , H01L27/11592
Abstract: A semiconductor device includes first conductive lines provided on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, second conductive lines spaced apart from the first conductive lines in a second direction parallel to the top surface of the substrate, a gate electrode disposed between the first and second conductive lines and extended in the first direction, a plurality of channel patterns provided to enclose a side surface of the gate electrode and spaced apart from each other in the first direction, a ferroelectric pattern between each of the channel patterns and the gate electrode, and a gate insulating pattern between each of the channel patterns and the ferroelectric pattern. Each of the channel patterns is connected to a corresponding one of the first conductive lines and a corresponding one of the second conductive lines.
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公开(公告)号：US20220406848A1
公开(公告)日：2022-12-22
申请号：US17840213
申请日：2022-06-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyuncheol KIM , Yongseok KIM , Dongsoo WOO , Kyunghwan LEE
Abstract: A semiconductor memory device includes a plurality of semiconductor patterns extending in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including a first source/drain area, a channel area, and a second source/drain area arranged in the first horizontal direction; a plurality of gate insulating layers covering upper surfaces or side surfaces of the channel areas; a plurality of word lines on the upper surfaces or the side surfaces of the channel areas; and a plurality of resistive switch units respectively connected to first sidewalls of the semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including a first electrode, a second electrode, and a resistive switch material layer between the first and second electrodes and including carbon nanotubes.
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Patent Agency Ranking
公开(公告)号：US20210358913A1
公开(公告)日：2021-11-18
申请号：US17092593
申请日：2020-11-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol KIM , Yongseok KIM , Huijung KIM , Satoru YAMADA , Sungwon YOO , Kyunghwan LEE , Jaeho HONG
IPC: H01L27/102 , H01L29/74
Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.
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公开(公告)号：US20190053080A1
公开(公告)日：2019-02-14
申请号：US16054504
申请日：2018-08-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok RYU , Yongseok KIM , Peng XUE , Hyunkyu YU , Sangwon CHOI , Kuyeon WHANG
Abstract: The fifth generation (5G) or pre-5G communication system for supporting a higher data rate after a fourth generation (4G) communication system like a long term evolution (LTE) are provided. An uplink transmission method is provided, which can increase an uplink coverage through improvement of reception reliability of uplink control information and data information.
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公开(公告)号：US20240306398A1
公开(公告)日：2024-09-12
申请号：US18594350
申请日：2024-03-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongseok KIM , Yukio HAYAKAWA , Minjun LEE , Bongyong LEE , Siyeon CHO
Abstract: A three-dimensional non-volatile memory device includes a plurality of horizontal word lines spaced apart from each other in a vertical direction, a pillar gate electrode buried in a first channel hole that passes through the horizontal word lines in the vertical direction, and a first dielectric layer disposed between the pillar gate electrode and the horizontal word lines in a cross section. The pillar gate electrode, the first dielectric layer, and the horizontal word lines correspond to memory cells including a plurality of variable capacitors spaced apart from each other in a vertical direction. The memory device further includes a selection transistor on the pillar gate electrode and the horizontal word lines and connected to one end of the pillar gate electrode, and a storage transistor under the pillar gate electrode and the horizontal word lines and connected to another end of the pillar gate electrode.
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公开(公告)号：US20240170072A1
公开(公告)日：2024-05-23
申请号：US18510074
申请日：2023-11-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Suhwan LIM , Kyunghwan LEE , Yongseok KIM
CPC classification number: G11C16/16 , G11C16/0433 , G11C16/24 , G11C16/32
Abstract: A storage device capable of performing erase operations in units smaller than blocks may include nonvolatile memory, and processing circuitry configured to, apply an erase voltage to a first bit line of the plurality of bit lines of at least one memory block of the plurality of memory blocks, apply an erase prohibition voltage to a second bit line of the plurality of bit lines, the erase prohibition voltage having a voltage level lower than a voltage level of the erase voltage, and float the common source line to cause an erasure of data stored in at least one first memory cell included in at least one first cell string connected to the first bit line by floating the common source line, and preserve data stored in at least one second memory cell included in at least one second cell string connected to the second bit line.
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公开(公告)号：US20230371270A1
公开(公告)日：2023-11-16
申请号：US18315181
申请日：2023-05-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol KIM , Yongseok KIM , Kiheun LEE , Daewon HA
CPC classification number: H10B51/30 , H10B51/10 , H01L29/40111
Abstract: A memory device may include a channel region, a conductive electrode disposed on the channel region, and a data storage structure disposed between the channel region and the conductive electrode. The data storage structure includes a first dielectric layer and a second dielectric layer disposed on the first dielectric layer, the second dielectric layer includes a ferroelectric region and a barrier dielectric region on the ferroelectric region, the ferroelectric region includes a first material, and the barrier dielectric region includes a second material formed by nitriding or oxidizing the first material.
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