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公开(公告)号：US20240306398A1
公开(公告)日：2024-09-12
申请号：US18594350
申请日：2024-03-04
发明人： Yongseok KIM , Yukio HAYAKAWA , Minjun LEE , Bongyong LEE , Siyeon CHO
摘要： A three-dimensional non-volatile memory device includes a plurality of horizontal word lines spaced apart from each other in a vertical direction, a pillar gate electrode buried in a first channel hole that passes through the horizontal word lines in the vertical direction, and a first dielectric layer disposed between the pillar gate electrode and the horizontal word lines in a cross section. The pillar gate electrode, the first dielectric layer, and the horizontal word lines correspond to memory cells including a plurality of variable capacitors spaced apart from each other in a vertical direction. The memory device further includes a selection transistor on the pillar gate electrode and the horizontal word lines and connected to one end of the pillar gate electrode, and a storage transistor under the pillar gate electrode and the horizontal word lines and connected to another end of the pillar gate electrode.
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公开(公告)号：US20230329012A1
公开(公告)日：2023-10-12
申请号：US18149929
申请日：2023-01-04
发明人： Bongyong LEE , Taeyoung KIM , Hyunmog PARK , Siyeon CHO
摘要： A semiconductor device may include a first substrate structure including a substrate, circuit elements on the substrate, and first bonding layers on the circuit elements, and a second substrate structure on the first substrate structure. The second substrate structure may include a plate layer, an intermediate insulating layer below the plate layer and including silicon nitride, gate electrodes below the intermediate insulating layer and stacked to be spaced apart from each other in a vertical direction, a channel structure in a channel hole passing through the intermediate insulating layer and the gate electrodes and including a semiconductor layer, and second bonding layers connected to the first bonding layers. The channel hole may have a first width in a first portion passing through the gate electrodes and a second width, wider than the first width, in a second portion passing through the intermediate insulating layer.
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公开(公告)号：US20230139541A1
公开(公告)日：2023-05-04
申请号：US17969942
申请日：2022-10-20
发明人： Bongyong LEE , Seungwon LEE
IPC分类号： H01L27/11582 , H01L25/065 , H01L25/18 , H01L23/00
摘要： A semiconductor device includes a substrate; a stack structure including a first gate layer, a first interlayer insulating layer, and a second gate layer; and a channel structure penetrating through the stack structure and in contact with the substrate, the channel structure including a channel layer, a vertical tunneling layer surrounding the channel layer, a charge storage pattern on an outer surface of the vertical tunneling layer, and a blocking pattern on an outer surface of the charge storage pattern, the charge storage pattern includes first and second charge storage material layers vertically spaced apart and adjacent to the gate layers, the blocking pattern includes vertically spaced blocking material layers between the charge storage material layers and the gate layers, and the blocking pattern contacts the outer surface of the charge storage pattern and includes a vertical protrusion extending longer than the outer surface of the charge storage pattern.
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公开(公告)号：US20190341456A1
公开(公告)日：2019-11-07
申请号：US16515412
申请日：2019-07-18
发明人： Moorym CHOI , Bongyong LEE , Junhee LIM
IPC分类号： H01L29/10 , H01L29/78 , H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： A three-dimensional semiconductor memory device includes common source regions, an electrode structure between the common source regions, first channel structures penetrating the electrode structure, and second channel structures between the first channel structures and penetrating the electrode structures. The electrode structure includes electrodes vertically stacked on a substrate. The first channel structures include a first semiconductor pattern and a first vertical insulation layer. The second channel structures include a second vertical insulation layer surrounding a second semiconductor pattern. The second vertical insulation layer has a bottom surface lower than a bottom surface of the first vertical insulation layer.
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公开(公告)号：US20230337438A1
公开(公告)日：2023-10-19
申请号：US18152310
申请日：2023-01-10
发明人： Hyunmog PARK , Bongyong LEE
摘要： A semiconductor device includes gate electrodes extending in a first direction, first and second vertical structures passing through the gate electrodes, a first upper interconnection, and a second upper interconnection structure, the first and second vertical structures including a back gate electrode, a ferroelectric material layer, a channel layer, and a gate insulating layer, the first upper interconnection structure including bit lines extending in a second direction, a first contact plug connected to a lower surface of a first back gate electrode of the first vertical structure, and a first back gate interconnection extending between the bit lines in the second direction and connected to the first contact plug, and the second upper interconnection structure including a second contact plug connected to an upper surface of a second back gate electrode of the second vertical structure, and a second back gate interconnection extending in the second direction and connected to the second contact plug.
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公开(公告)号：US20220216233A1
公开(公告)日：2022-07-07
申请号：US17702967
申请日：2022-03-24
发明人： Bongyong LEE , Taehun KIM , Minkyung BAE , Myunghun WOO , Doohee HWANG
IPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11573 , H01L27/11529 , H01L27/1157 , H01L27/11524
摘要： A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.
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公开(公告)号：US20230413575A1
公开(公告)日：2023-12-21
申请号：US18192994
申请日：2023-03-30
发明人： Bongyong LEE , Yongseok KIM
摘要： A 3D FeRAM device includes a capacitor structure including a first capacitor electrode on a substrate, the first capacitor electrode extending in a vertical direction substantially perpendicular to an upper surface of the substrate, a ferroelectric pattern surrounding a sidewall of the first capacitor electrode, and second capacitor electrodes surrounding and contacting an outer sidewall of the ferroelectric pattern, the second capacitor electrodes being spaced apart from each other in the vertical direction, an access transistor including a channel layer on the first capacitor electrode, a gate insulation layer surrounding an outer sidewall of the channel layer, and a gate electrode surrounding an outer sidewall of the gate insulation layer, a conductive pad on the channel layer, a contact plug on the conductive pad, and a bit line on the contact plug.
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公开(公告)号：US20210065809A1
公开(公告)日：2021-03-04
申请号：US16821225
申请日：2020-03-17
发明人： Doohee HWANG , Taehun KIM , Minkyung BAE , Myunghun WOO , Bongyong LEE
摘要： A semiconductor device includes a source layer; a plurality of channel structures; a plurality of gate electrodes; and a common source line. At least one of the plurality of gate electrodes provides a GIDL line. For an erasing operation, an erasing voltage applied to the common source line reaches a target voltage, and, after the erasing voltage reaches the target voltage, a step increment voltage is applied to the erasing voltage, such that the erasing voltage has a voltage level higher than a voltage level of the target voltage. After the step increment voltage has been applied for a desired time period, the voltage level of the erasing voltage is decreased to the target voltage level for the remainder of the erasing operation.
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公开(公告)号：US20230292630A1
公开(公告)日：2023-09-14
申请号：US17966183
申请日：2022-10-14
发明人： Siyeon CHO , Taeyoung KIM , Hyunmog PARK , Bongyong LEE , Yukio HAYAKAWA
CPC分类号： H01L43/04 , G11C11/161 , G11C11/18 , H01L27/222 , H01L43/06 , H01L43/10
摘要： A magnetic memory device includes a loop-type magnetic track having a first part and a second part that are arranged in a counterclockwise direction, a first conductive line on a top surface of the first part, and a second conductive line on a bottom surface of the second part. The magnetic track includes a lower magnetic layer, a spacer layer, and an upper magnetic layer that are sequentially stacked. Each of the first and second conductive lines includes heavy metal. Each of the first and second conductive lines is configured to generate spin-orbit torque caused by current that flows therein. The spin-orbit torque causes magnetic domains in the magnetic track to move in a clockwise direction or in the counterclockwise direction.
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公开(公告)号：US20130194872A1
公开(公告)日：2013-08-01
申请号：US13753677
申请日：2013-01-30
发明人： Jaesung SIM , Bongyong LEE
CPC分类号： G11C16/26 , G11C7/04 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/06 , G11C2216/14
摘要： Disclosed is a nonvolatile memory device which includes a memory cell connected to a bit line and a word line; a page buffer electrically connected to the bit line and sensing data stored in the memory cell; and a control logic controlling the page buffer to vary a develop time of the bit line or a sensing node connected to the bit line according to a current temperature during a read operation.
摘要翻译： 公开了一种非易失性存储器件，其包括连接到位线和字线的存储单元; 电位连接到位线并感测存储在存储单元中的数据的页缓冲器; 以及控制逻辑控制页缓冲器，以在读操作期间根据当前温度来改变位线或连接到位线的感测节点的显影时间。
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