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公开(公告)号：US11003449B2
公开(公告)日：2021-05-11
申请号：US16256266
申请日：2019-01-24
发明人： Moo-Kyoung Chung , Woong Seo , Ho-Young Kim , Soo-Jung Ryu , Dong-Hoon Yoo , Jin-Seok Lee , Yeon-Gon Cho , Chang-Moo Kim , Seung-Hun Jin
IPC分类号： G06F9/30
摘要： A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations.
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公开(公告)号：US10733764B2
公开(公告)日：2020-08-04
申请号：US15622927
申请日：2017-06-14
发明人： Sang-Heon Lee , Yeon-Gon Cho , Soo-Jung Ryu
摘要： A texture processing method and apparatus that obtains information about a first data loss amount that occurred during a texture compression process. A determination is made regarding a second data loss amount that allowable during a texture filtering process based on the obtained information regarding the first data loss amount. Texture filtering is then performed by using the second data loss amount. At least one processor determines the second data loss amount based on a difference between the third data loss amount and the first data loss amount.
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公开(公告)号：US10585709B2
公开(公告)日：2020-03-10
申请号：US14800002
申请日：2015-07-15
发明人： Woong Seo , Yeon-Gon Cho , Soo-Jung Ryu , Seok-Woo Song , John Dongjun Kim , Min-Seok Lee
摘要： An apparatus and a job scheduling method are provided. For example, the apparatus is a multi-core processing apparatus. The apparatus and method minimize performance degradation of a core caused by sharing resources by dynamically managing a maximum number of jobs assigned to each core of the apparatus. The apparatus includes at least one core including an active cycle counting unit configured to store a number of active cycles and a stall cycle counting unit configured to store a number of stall cycles and a job scheduler configured to assign at least one job to each of the at least one core, based on the number of active cycles and the number of stall cycles. When the ratio of the number of stall cycles to a number of active cycles for a core is too great, the job scheduler assigns fewer jobs to that core to improve performance.
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公开(公告)号：US20180144506A1
公开(公告)日：2018-05-24
申请号：US15622927
申请日：2017-06-14
发明人： Sang-Heon Lee , Yeon-Gon Cho , Soo-Jung Ryu
摘要： A texture processing method and apparatus that obtains information about a first data loss amount that occurred during a texture compression process. A determination is made regarding a second data loss amount that allowable during a texture filtering process based on the obtained information regarding the first data loss amount. Texture filtering is then performed by using the second data loss amount. At least one processor determines the second data loss amount based on a difference between the third data loss amount and the first data loss amount.
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公开(公告)号：US09886384B2
公开(公告)日：2018-02-06
申请号：US14931019
申请日：2015-11-03
发明人： Jun-Kyoung Kim , Dong-Hoon Yoo , Jeong-Wook Kim , Soo-Jung Ryu
IPC分类号： G06F12/00 , G06F12/0862 , G06F12/0875 , G06F9/38 , G06F9/45
CPC分类号： G06F12/0862 , G06F8/4442 , G06F9/383 , G06F12/0875 , G06F2212/452 , G06F2212/6026 , G06F2212/6028
摘要： The present examples relate to prefetching, and to a cache control device for prefetching and a prefetching method using the cache control device, wherein the cache control device analyzes a memory access pattern of program code, inserts, into the program code, a prefetching command generated by encoding the analyzed access pattern, and executes the prefetching command inserted into the program code in order to prefetch data into a cache, thereby maximizing prefetching efficiency.
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公开(公告)号：US09507753B2
公开(公告)日：2016-11-29
申请号：US14694420
申请日：2015-04-23
发明人： Woong Seo , Han-Joon Kim , John Kim , Soo-Jung Ryu
IPC分类号： G06F15/80 , H04L12/773 , H04L12/721 , G06F15/173 , G06F9/445
CPC分类号： G06F15/80 , G06F9/44505 , G06F15/17312 , H04L45/06 , H04L45/60
摘要： Provided is a processor with a data transfer structure that is excellent in performance and efficiency. According to an aspect, the processor may include a plurality of processing elements, a plurality of routers respectively connected to the processing elements, and a plurality of connection links formed between the routers such that data is transferred between the processors via a network.
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公开(公告)号：US09405349B2
公开(公告)日：2016-08-02
申请号：US14287515
申请日：2014-05-27
发明人： Woong Seo , Yeon-Gon Cho , Soo-Jung Ryu , Seok-Woo Song , John Dongjun Kim , Min-Seok Lee
CPC分类号： G06F1/3234 , G06F1/3287 , G06F1/329 , G06F9/4893 , Y02D10/171 , Y02D10/24
摘要： A multi-core apparatus includes cores each including an active cycle counting unit configured to store an active cycle count, and a stall cycle counting unit configured to store a stall cycle count. The multi-core apparatus further includes a job scheduler configured to determine an optimal number of cores in an active state based on state information received from each of the cores, and adjust power to maintain the optimal number of cores.
摘要翻译： 多核装置包括各自包括被配置为存储活动周期计数的活动周期计数单元的核，以及配置成存储失速循环计数的失速循环计数单元。 多核装置还包括：作业调度器，被配置为基于从每个核接收到的状态信息来确定活动状态的最佳核数，并调整功率以维持最佳核数。
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公开(公告)号：US09256949B2
公开(公告)日：2016-02-09
申请号：US13919384
申请日：2013-06-17
发明人： Sang-Heon Lee , Soo-Jung Ryu , Yeon-Gon Cho , Do-Hyun Kim , Yeong-Gil Shin , Byeong-Hun Lee
IPC分类号： G06T7/00
CPC分类号： G06T7/0081 , G06T7/11 , G06T2207/10081
摘要： A region growing apparatus using multi-core includes a plurality of cores, each core including an operation controller configured to perform an operation for region growing of a 2D pixel region or 3D pixel region and an inner memory configured to store a queue associated with a seed pixel as a target of the operation; and a shared memory connected to the plurality of cores over a network and shared by the plurality of cores.
摘要翻译： 使用多核的区域生长装置包括多个核心，每个核心包括被配置为执行2D像素区域或3D像素区域的区域生长的操作的操作控制器和被配置为存储与种子相关联的队列的内部存储器 像素作为操作的目标; 以及通过网络连接到所述多个核并由所述多个核共享的共享存储器。
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公开(公告)号：US09042392B2
公开(公告)日：2015-05-26
申请号：US13645800
申请日：2012-10-05
发明人： Woong Seo , Han-Joon Kim , John Kim , Soo-Jung Ryu
IPC分类号： H04L12/28 , H04L12/773 , H04L12/721 , G06F15/173
CPC分类号： G06F15/80 , G06F9/44505 , G06F15/17312 , H04L45/06 , H04L45/60
摘要： Provided is a processor with a data transfer structure that is excellent in performance and efficiency. According to an aspect, the processor may include a plurality of processing elements, a plurality of routers respectively connected to the processing elements, and a plurality of connection links formed between the routers such that data is transferred between the processors via a network.
摘要翻译： 提供了具有优异性能和效率的数据传输结构的处理器。 根据一个方面，处理器可以包括多个处理元件，分别连接到处理元件的多个路由器，以及形成在路由器之间的多个连接链路，使得数据经由网络在处理器之间传送。
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公开(公告)号：US10120833B2
公开(公告)日：2018-11-06
申请号：US14165881
申请日：2014-01-28
发明人： Woong Seo , Yeon-Gon Cho , Soo-Jung Ryu
摘要： Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit.
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