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12 条记录 (耗时 0.018 秒)

    System-on-chip, mobile terminal, and method for operating the system-on-chip
    1.
    发明授权
    System-on-chip, mobile terminal, and method for operating the system-on-chip 有权

    公开(公告)号：US10592454B2

    公开(公告)日：2020-03-17

    申请号：US16034470

    申请日：2018-07-13

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jae-Youl Kim ,  Chih Jen Lin ,  Jinook Song ,  Sungjae Lee ,  Hyun-ki Koo ,  Donghyeon Ham

    IPC分类号： G06F13/40 ,  G06F13/16 ,  G06T1/20

    摘要： A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.

    System-on-chip, mobile terminal, and method for operating the system-on-chip
    10.
    发明授权
    System-on-chip, mobile terminal, and method for operating the system-on-chip 有权

    公开(公告)号：US10025741B2

    公开(公告)日：2018-07-17

    申请号：US14995179

    申请日：2016-01-13

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jae-Youl Kim ,  Chih Jen Lin ,  Jinook Song ,  Sungjae Lee ,  Hyun-ki Koo ,  Donghyeon Ham

    IPC分类号： G06F13/00 ,  G06F13/36 ,  G06F13/40 ,  G06F13/16 ,  G06T1/20

    摘要： A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.