公开(公告)号：US12198778B2

公开(公告)日：2025-01-14

申请号：US18351709

申请日：2023-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Chung ,  Hyeongkon Bae ,  Myungjae Chung

IPC: G11C29/52 ,  G06F11/10 ,  G06F13/16 ,  G11C11/408

Abstract: A memory controller that controls a memory module including a plurality of memory chips, the memory controller including an error correction circuit including an encoding circuit and a processor to control the error correction circuit. The encoding circuit, in a write operation, divides a user data set into data units, generates data flags indicating types of the data units, generates data parities based on the data units, generates flag parities based on the data flags, generates an encoded user data set by using at least one null data unit in which all or half of included data bits are zero, as a data duplication space for duplicating a valid data unit, generates a codeword set by interleaving the encoded user data set, the data parities, the data flags, the flag parities and a null bit bit-wisely, and transmits the codeword set to the memory module.

公开(公告)号：US12019500B2

公开(公告)日：2024-06-25

申请号：US17839402

申请日：2022-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Chung ,  Seunghun Choi

IPC: G06F1/3296 ,  G06F1/20 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/329 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F1/3296 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/329 ,  G06F9/30083 ,  G06F9/3836 ,  G06F9/4893 ,  G06F1/206 ,  Y02D10/00

Abstract: An integrated circuit includes; a core configured to process an instruction in accordance with a voltage-frequency level, an instruction complexity calculation circuit configured to calculate an instruction complexity for at least one instruction to-be-processed after a reference time in relation to heating information related to the core acquired before the reference time, wherein the instruction complexity calculation circuit is further configured to generate a control signal corresponding to the instruction complexity, and a dynamic voltage and frequency scaling (DVFS) controller configured to adjust the voltage-frequency level after the reference time in response to the control signal.

公开(公告)号：US20240170089A1

公开(公告)日：2024-05-23

申请号：US18351709

申请日：2023-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Chung ,  Hyeongkon Bae ,  Myungjae Chung

IPC: G11C29/52 ,  G11C11/408

CPC classification number: G11C29/52 ,  G11C11/4087

Abstract: A memory controller that controls a memory module including a plurality of memory chips, the memory controller including an error correction circuit including an encoding circuit and a processor to control the error correction circuit. The encoding circuit, in a write operation, divides a user data set into data units, generates data flags indicating types of the data units, generates data parities based on the data units, generates flag parities based on the data flags, generates an encoded user data set by using at least one null data unit in which all or half of included data bits are zero, as a data duplication space for duplicating a valid data unit, generates a codeword set by interleaving the encoded user data set, the data parities, the data flags, the flag parities and a null bit bit-wisely, and transmits the codeword set to the memory module.