公开(公告)号：US09123655B2

公开(公告)日：2015-09-01

申请号：US14190797

申请日：2014-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Hwan Oh ,  Yu-Ra Kim ,  Tae-Sun Kim ,  Kwang-Sub Yoon

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L21/3086 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/32139

Abstract: A method of manufacturing a layer pattern of a semiconductor device, the method including forming an anti-reflective coating (ARC) layer on an etching object layer such that the ARC layer includes a polymer having an imide group; forming a photoresist pattern on the ARC layer; wet etching portions of the ARC layer exposed by the photoresist pattern to form an ARC layer pattern; and etching the etching object layer using the photoresist pattern as an etch mask to form the layer pattern.

Abstract translation: 一种制造半导体器件的层图案的方法，所述方法包括在蚀刻对象层上形成抗反射涂层（ARC）层，使得ARC层包括具有酰亚胺基团的聚合物; 在ARC层上形成光刻胶图案; 通过光致抗蚀剂图案曝光的ARC层的湿蚀刻部分以形成ARC层图案; 并使用光致抗蚀剂图案蚀刻蚀刻对象层作为蚀刻掩模以形成层图案。

公开(公告)号：US10338134B2

公开(公告)日：2019-07-02

申请号：US15333699

申请日：2016-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul Jun ,  Yun-Bo Yang ,  Dong-Ho Lee ,  Tae-Hwan Oh ,  Dong-Han Yoon

IPC: G01R31/28 ,  H05K1/11 ,  H05K1/02 ,  H05K1/18 ,  H01L25/07 ,  G01R31/3185

Abstract: In an interface board for testing a multichip package, the multichip package includes a first type semiconductor chip and a second type semiconductor chip, the interface board includes a first surface facing the multichip package and a second surface facing a test apparatus, the first surface includes upper terminals that are electrically connected to terminals of the multichip package, the second surface includes lower terminals that are electrically connected to the test apparatus, and the upper terminals include a first upper terminal group for testing the first type semiconductor chip and a second upper terminal group for testing whether a crack defect exists in the second type semiconductor chip.

公开(公告)号：US20170278745A1

公开(公告)日：2017-09-28

申请号：US15621618

申请日：2017-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Su Kim ,  Dong-Woon Park ,  Tae-Hoi Park ,  Yong-Kug Bae ,  Tae-Hwan Oh ,  Chang-Hoon Lee ,  Boo-Hyun Ham

IPC: H01L21/768 ,  H01L27/02 ,  G03F7/20 ,  H01L21/8234

CPC classification number: H01L21/76816 ,  G03F7/70633 ,  G03F7/70683 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207

Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.