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    SEMICONDUCTOR PACKAGES
    3.
    发明申请
    SEMICONDUCTOR PACKAGES 有权

    公开(公告)号：US20220278049A1

    公开(公告)日：2022-09-01

    申请号：US17664132

    申请日：2022-05-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joonsung Kim ,  Doohwan Lee ,  Taeho Ko ,  Bongsoo Kim ,  Seokbong Park

    IPC: H01L23/538 ,  H01L23/31 ,  H01L23/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01P3/08 ,  H01P11/00 ,  H01L23/29

    Abstract: A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.

    FAN-OUT SEMICONDUCTOR PACKAGE
    5.
    发明申请
    FAN-OUT SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20200161204A1

    公开(公告)日：2020-05-21

    申请号：US16681320

    申请日：2019-11-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joonsung Kim ,  Doohwan Lee ,  Jinseon Park

    IPC: H01L23/31 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00

    Abstract: A fan-out semiconductor package includes a semiconductor chip, an encapsulant covering the semiconductor chip, a connection structure disposed below the semiconductor chip, and first and second metal pattern layers disposed on different levels on the semiconductor chip, wherein the first metal pattern layer is provided to electrically connect to an electrical connection member such as a frame, provided for electrical connection of the package in a vertical direction by a path via the second metal pattern layer.

    Fan-out semiconductor packages
    6.
    发明授权
    Fan-out semiconductor packages 有权

    公开(公告)号：US12159833B2

    公开(公告)日：2024-12-03

    申请号：US18151731

    申请日：2023-01-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joonsung Kim ,  Khaile Kim

    IPC: H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

    Abstract: A fan-out semiconductor package includes a frame substrate having a through hole therein, a semiconductor chip in the through hole, wherein the semiconductor chip includes a chip body, a chip pad on a surface of the chip body and a passivation layer on the chip body and on the chip pad, an encapsulation layer on side surfaces of the semiconductor chip within the through hole, and a guard ring on the passivation layer and on an edge portion of the chip body.

    SEMICONDUCTOR PACKAGE
    7.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240363542A1

    公开(公告)日：2024-10-31

    申请号：US18765648

    申请日：2024-07-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joonsung Kim

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L23/522

    CPC classification number: H01L23/5383 ,  H01L23/3121 ,  H01L23/34 ,  H01L23/5226 ,  H01L23/5386 ,  H01L24/08 ,  H01L23/3171 ,  H01L2224/08235

    Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate and a first chip pad on a first bottom surface of the first semiconductor substrate, a second semiconductor chip including a second semiconductor substrate and a second chip pad on a second top surface of the second semiconductor substrate, a lower redistribution structure provided under the first semiconductor chip and the second semiconductor chip, the lower redistribution structure including a lower redistribution pattern, the lower redistribution pattern including a first lower redistribution via pattern contacting the first chip pad, a molding layer covering the first semiconductor chip and the second semiconductor chip, an upper redistribution structure including an upper redistribution pattern, the upper redistribution pattern including a first upper redistribution via pattern connected to the second chip pad, and a conductive connection structure electrically connecting the lower redistribution pattern to the upper redistribution pattern.

    Fan-out semiconductor packages
    10.
    发明授权
    Fan-out semiconductor packages 有权

    公开(公告)号：US11574868B2

    公开(公告)日：2023-02-07

    申请号：US17022718

    申请日：2020-09-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joonsung Kim ,  Khaile Kim

    IPC: H01L23/00 ,  H01L23/528 ,  H01L23/31 ,  H01L23/498

    Abstract: A fan-out semiconductor package includes a frame substrate having a through hole therein, a semiconductor chip in the through hole, wherein the semiconductor chip includes a chip body, a chip pad on a surface of the chip body and a passivation layer on the chip body and on the chip pad, an encapsulation layer on side surfaces of the semiconductor chip within the through hole, and a guard ring on the passivation layer and on an edge portion of the chip body.

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