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公开(公告)号：US09240393B2
公开(公告)日：2016-01-19
申请号：US14450005
申请日：2014-08-01
发明人： Cheeman Yu , Zhong Lu , Gursharan Singh , Wei Gu
IPC分类号： H01L25/065 , H01L23/31 , H01L25/00 , H01L21/66
CPC分类号： H01L25/0657 , H01L22/14 , H01L23/3135 , H01L24/73 , H01L25/50 , H01L2224/04042 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45139 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2224/78301 , H01L2224/85205 , H01L2224/92247 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2924/15311 , H01L2924/15313 , H01L2924/181 , H01L2924/19107 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device including two or more die stacks mounted to a substrate. The first die stack is mounted, at least partially encapsulated, and then tested. If the first die stack functions within predefined parameters, a second die stack is mounted on the first die stack, and then the device may undergo a second encapsulation process. Testing the first die stack before mounting the second improves yield by identifying faulty semiconductor die before all die are mounted within the semiconductor device.
摘要翻译： 一种半导体器件，包括安装在衬底上的两个或更多个管芯堆叠。 安装第一个模具堆叠，至少部分封装，然后测试。 如果第一裸片堆栈在预定义参数内起作用，则第二裸片堆叠被安装在第一裸片叠上，然后该装置可经历第二封装处理。 在安装第二芯片堆叠之前测试第一个裸片堆叠通过在所有裸片安装在半导体器件中之前识别有缺陷的半导体裸片来提高产量。
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公开(公告)号：US10811386B2
公开(公告)日：2020-10-20
申请号：US15704996
申请日：2017-09-14
发明人： Chin Tien Chiu , Hem Takiar , Gursharan Singh , Fisher Yu , C C Liao
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00 , H01L23/31
摘要： The present technology relates to a semiconductor device. The semiconductor device comprises: a plurality of dies stacked on top of each other, each of the dies comprising a first major surface, an IO conductive pattern on the first major surface and extended to a minor surface substantially perpendicular to the major surfaces to form at least one IO electrical contact on the minor surface, and the plurality of dies aligned so that the corresponding minor surfaces of all dies substantially coplanar with respect to each other to form a common flat sidewall, and a plurality of IO routing traces formed over the sidewall and at least partially spaced away from the sidewall. The plurality of IO routing traces are spaced apart from each other in a first direction on the sidewall, and each of IO routing traces is electrically connected to a respective IO electrical contact and extended across the sidewall in a second direction substantially perpendicular to the first direction on the sidewall.
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公开(公告)号：US20180114773A1
公开(公告)日：2018-04-26
申请号：US15704984
申请日：2017-09-14
发明人： Chin Tien Chiu , Tiger Tai , Ken Qian , CC Liao , Hem Takiar , Gursharan Singh
IPC分类号： H01L25/065 , H01L25/00
CPC分类号： H01L25/0652 , H01L24/05 , H01L24/16 , H01L24/24 , H01L24/25 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/82 , H01L25/50 , H01L2224/02371 , H01L2224/02377 , H01L2224/0401 , H01L2224/05548 , H01L2224/13144 , H01L2224/13147 , H01L2224/14131 , H01L2224/16137 , H01L2224/16145 , H01L2224/24051 , H01L2224/24105 , H01L2224/24147 , H01L2224/244 , H01L2224/245 , H01L2224/2512 , H01L2224/25175 , H01L2224/2518 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/73207 , H01L2224/73209 , H01L2224/73227 , H01L2224/73253 , H01L2224/73257 , H01L2224/73267 , H01L2224/82051 , H01L2224/82106 , H01L2224/82948 , H01L2225/06506 , H01L2225/06513 , H01L2225/06551 , H01L2225/06555 , H01L2924/01079 , H01L2924/01029 , H01L2924/01013 , H01L2924/00012 , H01L2924/00014
摘要： The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.
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公开(公告)号：US11031371B2
公开(公告)日：2021-06-08
申请号：US15704984
申请日：2017-09-14
发明人： Chin Tien Chiu , Tiger Tai , Ken Qian , C C Liao , Hem Takiar , Gursharan Singh
IPC分类号： H01L25/065 , H01L23/00 , H01L25/18 , H01L25/00
摘要： The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.
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公开(公告)号：US20150061157A1
公开(公告)日：2015-03-05
申请号：US14450005
申请日：2014-08-01
发明人： Cheeman Yu , Zhong Lu , Gursharan Singh , Wei Gu
IPC分类号： H01L25/065 , H01L21/56 , H01L21/66 , H01L23/31
CPC分类号： H01L25/0657 , H01L22/14 , H01L23/3135 , H01L24/73 , H01L25/50 , H01L2224/04042 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45139 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2224/78301 , H01L2224/85205 , H01L2224/92247 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2924/15311 , H01L2924/15313 , H01L2924/181 , H01L2924/19107 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device including two or more die stacks mounted to a substrate. The first die stack is mounted, at least partially encapsulated, and then tested. If the first die stack functions within predefined parameters, a second die stack is mounted on the first die stack, and then the device may undergo a second encapsulation process. Testing the first die stack before mounting the second improves yield by identifying faulty semiconductor die before all die are mounted within the semiconductor device.
摘要翻译： 一种半导体器件，包括安装到衬底上的两个或更多个管芯堆叠。 安装第一个模具堆叠，至少部分封装，然后进行测试。 如果第一裸片堆栈在预定义参数内起作用，则第二裸片堆叠被安装在第一裸片叠上，然后该装置可经历第二封装处理。 在安装第二芯片堆叠之前测试第一个裸片堆叠通过在所有裸片安装在半导体器件中之前识别有缺陷的半导体裸片来提高产量。
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公开(公告)号：US20180114777A1
公开(公告)日：2018-04-26
申请号：US15704996
申请日：2017-09-14
发明人： Chin Tien Chiu , Hem Takiar , Gursharan Singh , Fisher Yu , CC Liao
IPC分类号： H01L25/065 , H01L23/31
摘要： The present technology relates to a semiconductor device. The semiconductor device comprises: a plurality of dies stacked on top of each other, each of the dies comprising a first major surface, an IO conductive pattern on the first major surface and extended to a minor surface substantially perpendicular to the major surfaces to form at least one IO electrical contact on the minor surface, and the plurality of dies aligned so that the corresponding minor surfaces of all dies substantially coplanar with respect to each other to form a common flat sidewall, and a plurality of IO routing traces formed over the sidewall and at least partially spaced away from the sidewall. The plurality of IO routing traces are spaced apart from each other in a first direction on the sidewall, and each of IO routing traces is electrically connected to a respective IO electrical contact and extended across the sidewall in a second direction substantially perpendicular to the first direction on the sidewall.
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