公开(公告)号：US09985046B2

公开(公告)日：2018-05-29

申请号：US15180902

申请日：2016-06-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhenyu Lu ,  Jixin Yu ,  Koji Miyata ,  Makoto Yoshida ,  Johann Alsmeier ,  Hiro Kinoshita ,  Daxin Mao

IPC: H01L27/115 ,  H01L27/11582 ,  H01L21/66 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L23/528 ,  H01L23/522 ,  H01L23/544 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76801 ,  H01L22/20 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L2223/54426

Abstract: A linear mark extending perpendicular to a primary step direction of stepped terrace for a three-dimensional memory device can be employed as a reference feature for aligning a trimming material layer before initiating an etch-and-trim process sequence. The linear mark can be formed as a linear trench or a linear rail structure. The distance between a sidewall of each trimming material layer and the linear mark can be measured at multiple locations that are laterally spaced apart perpendicular to the primary step direction to provide statistically significant data points, which can be employed to provide an enhanced control of the staircase patterning process. Likewise, locations of patterned stepped surfaces can be measured at multiple locations to provide enhanced control of the locations of vertical steps in the stepped terrace.

公开(公告)号：US09859363B2

公开(公告)日：2018-01-02

申请号：US15155639

申请日：2016-05-16

Applicant: SANDISK TECHNOLOGIES, LLC.

Inventor： Zhenyu Lu ,  Kota Funayama ,  Chun-Ming Wang ,  Jixin Yu ,  Chenche Huang ,  Tong Zhang ,  Daxin Mao ,  Johann Alsmeier ,  Makoto Yoshida ,  Lauren Matsumoto

IPC: H01L29/06 ,  H01L21/76 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/24 ,  H01L27/112

CPC classification number: H01L29/0649 ,  H01L27/1128 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/2481

Abstract: A method of dividing drain select gate electrodes in a three-dimensional vertical memory device is provided. An alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.